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[Qemu-arm] [PATCH 04/13] target/arm: Mask PMU register writes based on P
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N |
Date: |
Fri, 29 Sep 2017 22:08:21 -0400 |
This is in preparation for enabling counters other than PMCCNTR
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ecf8c55..54070a3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -30,11 +30,6 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
hwaddr *phys_ptr, MemTxAttrs *txattrs, int
*prot,
target_ulong *page_size_ptr, uint32_t *fsr,
ARMMMUFaultInfo *fi);
-
-/* Definitions for the PMCCNTR and PMCR registers */
-#define PMCRD 0x8
-#define PMCRC 0x4
-#define PMCRE 0x1
#endif
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
@@ -876,6 +871,17 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
REGINFO_SENTINEL
};
+/* Definitions for the PMU registers */
+#define PMCRN 0xf800
+#define PMCRN_SHIFT 11
+#define PMCRD 0x8
+#define PMCRC 0x4
+#define PMCRE 0x1
+
+#define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN) >> PMCRN_SHIFT)
+/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
+#define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) - 1))
+
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
@@ -1060,14 +1066,14 @@ static void pmccfiltr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= (PMU_COUNTER_MASK(env) | (1 << 31));
env->cp15.c9_pmcnten |= value;
}
static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= (PMU_COUNTER_MASK(env) | (1 << 31));
env->cp15.c9_pmcnten &= ~value;
}
@@ -1115,14 +1121,14 @@ static void pmintenset_write(CPUARMState *env, const
ARMCPRegInfo *ri,
uint64_t value)
{
/* We have no event counters so only the C bit can be changed */
- value &= (1 << 31);
+ value &= PMU_COUNTER_MASK(env);
env->cp15.c9_pminten |= value;
}
static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= PMU_COUNTER_MASK(env);
env->cp15.c9_pminten &= ~value;
}
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies,
Inc.\nQualcomm Technologies, Inc. is a member of the\nCode Aurora Forum, a
Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v2 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0], Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N,
Aaron Lindsay <=
- [Qemu-arm] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 07/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 13/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2017/09/29