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Re: [Discuss-gnuradio] design flow question
From: |
Brian Padalino |
Subject: |
Re: [Discuss-gnuradio] design flow question |
Date: |
Wed, 27 Feb 2008 08:17:18 -0500 |
On Wed, Feb 27, 2008 at 8:07 AM, Neal Becker <address@hidden> wrote:
> Newb here. I'm wondering what you are using for a design flow to produce
> fpga code? I assume you are obtaining verilog? What tools are used to
> produce the verilog and work with it?
All Verilog source is written by hand - no HDL generators are being used.
The USRP uses an Altera Cyclone part and Quartus II for synthesis.
The upcoming USRP2 will have a Xilinx Spartan 3E (I believe) part and
will use WebPack/XST for synthesis.
Brian