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[Qemu-commits] [qemu/qemu] 8e2aa2: target/riscv: Update [m|h]tinst CSR i


From: Paolo Bonzini
Subject: [Qemu-commits] [qemu/qemu] 8e2aa2: target/riscv: Update [m|h]tinst CSR in riscv_cpu_d...
Date: Wed, 07 Sep 2022 06:50:26 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8e2aa21b0a0d434be2f53a9435fec4f63ec192c4
      
https://github.com/qemu/qemu/commit/8e2aa21b0a0d434be2f53a9435fec4f63ec192c4
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/instmap.h

  Log Message:
  -----------
  target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: dramforever <dramforever@live.com>
Message-Id: <20220630061150.905174-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9a1f054d5bd9acaa82b66e09309482cba9eced63
      
https://github.com/qemu/qemu/commit/9a1f054d5bd9acaa82b66e09309482cba9eced63
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Force disable extensions if priv spec version does not match

We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.

Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the device 
tree")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Message-Id: <20220630061150.905174-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3363277525958e173b4526f9dca225e125b1a5de
      
https://github.com/qemu/qemu/commit/3363277525958e173b4526f9dca225e125b1a5de
  Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M disas/riscv.c
    M target/riscv/insn16.decode
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: fix shifts shamt value for rv128c

For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction that does not change processor state.
For rv128c right shifts, the 6-bit shamt is in addition sign extended to
7 bits.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220710110451.245567-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6d00ffad4e9549086e80a47566ed5f3b4b8bb2dd
      
https://github.com/qemu/qemu/commit/6d00ffad4e9549086e80a47566ed5f3b4b8bb2dd
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: move zmmul out of the experimental properties

- Zmmul is ratified and is now version 1.0

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220710101546.3907-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e4b4f0b71ccbeb0157489c0904ba4957761528ff
      
https://github.com/qemu/qemu/commit/e4b4f0b71ccbeb0157489c0904ba4957761528ff
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: pass random seed to fdt

If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.

Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220613115810.178210-1-Jason@zx2c4.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0b572c8131998e7bcd048dbbbe78f95e6101d68d
      
https://github.com/qemu/qemu/commit/0b572c8131998e7bcd048dbbbe78f95e6101d68d
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Add check for supported privilege mode combinations

There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 756b0374dc37af2213e3b652fb3f50a4cc9acb24
      
https://github.com/qemu/qemu/commit/756b0374dc37af2213e3b652fb3f50a4cc9acb24
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: H extension depends on I extension

Add check for "H depends on an I base integer ISA with 32 x registers"
which is stated at the beginning of chapter 8 of the riscv-privileged
spec(draft-20220717)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 108c4f26ce441fe0fa0ee20c776e2b71706068be
      
https://github.com/qemu/qemu/commit/108c4f26ce441fe0fa0ee20c776e2b71706068be
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix checkpatch warning may triggered in csr_ops table

Fix the lines with over 80 characters

Fix the lines which are obviously misalgined with other lines in the
same group

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c126f83cd64883f7cb4be90a7fbf29e2be3bb9c7
      
https://github.com/qemu/qemu/commit/c126f83cd64883f7cb4be90a7fbf29e2be3bb9c7
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add check for csrs existed with U extension

Add umode/umode32 predicate for mcounteren, menvcfg/menvcfgh

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 62a09b9b4118ca42e79d9bd179daf7230462705b
      
https://github.com/qemu/qemu/commit/62a09b9b4118ca42e79d9bd179daf7230462705b
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix checks in hmode/hmode32

Add check for the implicit dependence between H and S

Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32 based on section 8.6.1 of riscv-privileged spec
(draft-20220717)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220718130955.11899-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5de124538b618c864508868eae505e77149649b7
      
https://github.com/qemu/qemu/commit/5de124538b618c864508868eae505e77149649b7
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Simplify the check in hmode to reuse the check in 
riscv_csrrw_check

Just add 1 to the effective privledge level when in HS mode, then reuse
the check of 'effective_priv < csr_priv' in riscv_csrrw_check to replace
the privilege level related check in hmode. Then, hmode will only check
whether H extension is supported.

When accessing Hypervior CSRs:
   1) If accessing from M privilege level, the check of
'effective_priv< csr_priv' passes, returns hmode(...) which will return
RISCV_EXCP_ILLEGAL_INST when H extension is not supported and return
RISCV_EXCP_NONE otherwise.
   2) If accessing from HS privilege level, effective_priv will add 1,
the check passes and also returns hmode(...) too.
   3) If accessing from VS/VU privilege level, the check fails, and
returns RISCV_EXCP_VIRT_INSTRUCTION_FAULT
   4) If accessing from U privilege level, the check fails, and returns
RISCV_EXCP_ILLEGAL_INST

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 780bb81bb3624b304d3226803b61e881777d183d
      
https://github.com/qemu/qemu/commit/780bb81bb3624b304d3226803b61e881777d183d
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M roms/opensbi

  Log Message:
  -----------
  roms/opensbi: Upgrade from v1.0 to v1.1

Upgrade OpenSBI from v1.0 to v1.1 and the pre-built bios images.

The v1.1 release includes the following commits:

5b99603 lib: utils/ipi: Fix size check in aclint_mswi_cold_init()
6dde435 lib: utils/sys: Extend HTIF library to allow custom base address
8257262 platform: sifive_fu740: do not use a global in da9063_reset/shutdown
fb688d9 platform: sifive_fu740: fix reset when watchdog is running
5d025eb lib: fix pointer of type 'void *' used in arithmetic
632f593 lib: sbi: Map only the counters enabled in hardware
3b7c204 lib: sbi: Disable interrupt during config matching
a26dc60 lib: sbi: Disable interrupt and inhibit counting in M-mode during init
5d53b55 Makefile: fix build with binutils 2.38
6ad8917 lib: fix compilation when strings.h is included
ce4c018 lib: utils/serial: Round UART8250 baud rate divisor to nearest integer
01250d0 include: sbi: Add AIA related CSR defines
8f96070 lib: sbi: Detect AIA CSRs at boot-time
65b4c7c lib: sbi: Use AIA CSRs for local interrupts when available
222132f lib: sbi: Add sbi_trap_set_external_irqfn() API
5f56314 lib: utils/irqchip: Allow multiple FDT irqchip drivers
1050940 include: sbi: Introduce nascent_init() platform callback
55e79f8 lib: sbi: Enable mie.MEIE bit for IPIs based on external interrupts.
9f73669 lib: utils/irqchip: Add IMSIC library
811da5c lib: utils/irqchip: Add FDT based driver for IMSIC
7127aaa lib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups()
9979265 lib: utils/irqchip: Add APLIC initialization library
3461219 lib: utils/irqchip: Add FDT based driver for APLIC
8e2ef4f lib: utils: Disable appropriate APLIC DT nodes in fdt_fixups()
3a69cc1 lib: sbi: fix typo in is_region_subset
f2ccf2f lib: sbi: verbose sbi_domain_root_add_memregion
f3f4604 lib: sbi: Add a simple external interrupt handling framework
4998a71 lib: utils: serial: Initial commit of xlnx-uartlite
2dfbd3c lib: pmp_set/pmp_get moved errors from runtime to compile time
b6b7220 firmware: Fix code for accessing hart_count and stack_size
d552fc8 lib: Add error messages via conditional compilation for the future
555bdb1 include: Use static asserts for SBI_PLATFORM_xxx_OFFSET defines
1b42d3a include: Use static asserts for SBI_SCRATCH_xxx_OFFSET defines
7924a0b include: Use static asserts for FW_DYNAMIC_INFO_xxx_OFFSET defines
722f80d include: Add defines for [m|h|s]envcfg CSRs
31fecad lib: sbi: Detect menvcfg CSR at boot time
47d6765 lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR
794986f lib: sbi: Enable Svpbmt extension in the menvcfg CSR
499601a lib: sbi: Add Smstateen extension defines
d44568a lib: sbi: Detect Smstateen CSRs at boot-time
3383d6a lib: irqchip/imsic: configure mstateen
5c5cbb5 lib: utils/serial: support 'reg-offset' property
c1e47d0 include: correct the definition of MSTATUS_VS
9cd95e1 lib: sbi/hart: preserve csr validation value
4035ae9 docs: pmu: Improve the PMU DT bindings
d62f6da lib: sbi: Implement Sstc extension
474a9d4 lib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not available
e576b3e include: sbi: Define SBI_PMU_HW_EVENT_MAX to 256
b0c9df5 lib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmf
1a754bb lib: sbi: Detect and print privileged spec version
5a6be99 lib: sbi: Remove 's' and 'u' from misa_string() output
5b8b377 lib: sbi: Update the name of ISA string printed at boot time
d4b563c lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart features
dbc3d8f lib: sbi: Remove MCOUNTINHIBT hart feature
97a17c2 lib: sbi: Remove MENVCFG hart feature
a6ab94f lib: sbi: Fix AIA feature detection
cad6c91 lib: sbi: Convert hart features into hart extensions
be4903a lib: sbi: Detect hart features only once for each hart
994ace3 lib: sbi: Add sbi_hart_update_extension() function
023f0ad lib: sbi_platform: Add callback to populate HART extensions
f726f2d Makefile: Allow generated C source to be anywhere in build directory
7fb474b Makefile: Add support for generating C array at compile time
73cf511 lib: utils/reset: Generate FDT reset driver list at compile-time
1e62705 lib: utils/serial: Generate FDT serial driver list at compile-time
bfeb305 lib: utils/timer: Generate FDT timer driver list at compile-time
3a69d12 lib: utils/irqchip: Generate FDT irqchip driver list at compile-time
4ee0c57 lib: utils/ipi: Generate FDT ipi driver list at compile-time
998ed43 lib: utils/i2c: Generate FDT i2c adapter driver list at compile-time
4eacd82 lib: utils/gpio: Generate FDT gpio driver list at compile-time
a3a3c60 platform: generic: Generate platform override module list at 
compile-time
9a7a677 platform: generic: Move Sifive platform overrides into own directory
851c14d lib: utils/irqchip: fix typo when checking for CPU node
90a9dd2 lib: utils/fdt: introduce fdt_node_is_enabled()
616da52 lib: utils: check if CPU node is enabled
575bb4e platform: generic: check if CPU node is enabled
1bc67db lib: utils/fdt: rename fdt_parse_max_hart_id
f067bb8 lib: sbi: fix system_opcode_insn
fab0379 lib: utils/fdt: Require match data to be const
295e5f3 lib: sbi_timer: Drop unnecessary get_platform_ticks wrapper
ff65bfe lib: sbi_illegal_insn: Constify illegal_insn_table
cb8271c lib: sbi_illegal_insn: Add emulation for fence.tso
adc3388 lib: sbi_trap: Redirect exception based on hedeleg
ce1d618 platform: generic: add overrides for vendor extensions
b20ed9f lib: sbi_hsm: Call a device hook during hart resume
79e42eb lib: sbi_hsm: Assume a consistent resume address
2ea7799 lib: irqchip/plic: Constify plic_data pointers
8c362e7 lib: irqchip/plic: Factor out a context init function
415ecf2 lib: irqchip/plic: Add context save/restore helpers
2b79b69 lib: irqchip/plic: Add priority save/restore helpers
69be3df lib: utils/irqchip: Add FDT wrappers for PLIC save/restore functions
5e56758 lib: utils/irqchip: Add wrapper for T-HEAD PLIC delegation
9dc5ec5 platform: Add HSM implementation for Allwinner D1
551c70c include: sbi: Add mtinst/htinst psuedoinstructions
187127f lib: sbi: Fixup tinst for exceptions in sbi_misaligned_*()
a07402a lib: sbi: Fix tval and tinst for sbi_get_insn()
c653001 lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bits
7738345 lib: utils/timer: Add a separate compatible for the D1 CLINT
d76a196 lib: irqchip/plic: fix typo in plic_warm_irqchip_init
6f1fe98 lib: utils/timer: Remove Allwinner D1 CLINT compatibles
c6fdbcf include: sbi: Change spec version to 1.0
3f66465 lib: pmu: allow to use the highest available counter
4489876 include: Bump-up version to 1.1

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220713090613.204046-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dec19f68130cda6c44c4eab4ed8c185c5ed40e5a
      
https://github.com/qemu/qemu/commit/dec19f68130cda6c44c4eab4ed8c185c5ed40e5a
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V

Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN")
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220717101543.478533-2-space.monkey.delivers@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 079520033facc70beee5eedee8d7a27a2a9261b4
      
https://github.com/qemu/qemu/commit/079520033facc70beee5eedee8d7a27a2a9261b4
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M docs/about/build-platforms.rst

  Log Message:
  -----------
  docs: List kvm as a supported accelerator on RISC-V

Since commit fbf43c7dbf18 ("target/riscv: enable riscv kvm accel"),
KVM accelerator is supported on RISC-V. Let's document it.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220719082635.3741878-1-bin.meng@windriver.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 355d5584de1129eec1c4043fdee1335010cfabb6
      
https://github.com/qemu/qemu/commit/355d5584de1129eec1c4043fdee1335010cfabb6
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/internals.h
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vv instructions

According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".

There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.

This is the first commit regarding the optional mask agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-1@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 265ecd4c62a008f3be351a75e1847cee9c71e380
      
https://github.com/qemu/qemu/commit/265ecd4c62a008f3be351a75e1847cee9c71e380
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vector load / store instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-2@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bce9a636beabbb2c538cdfca49592b04bfbf7e2c
      
https://github.com/qemu/qemu/commit/bce9a636beabbb2c538cdfca49592b04bfbf7e2c
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vx instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-3@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fd93045ebfa6ab07ce7017fb4095736c3f6f315a
      
https://github.com/qemu/qemu/commit/fd93045ebfa6ab07ce7017fb4095736c3f6f315a
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vector integer shift instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-4@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6e11d7eaa02c5834e5172d25e8c794ac5731b56e
      
https://github.com/qemu/qemu/commit/6e11d7eaa02c5834e5172d25e8c794ac5731b56e
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vector integer comparison 
instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-5@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 72e17a9f86098feb25d2c1f2af043dc5f9f211e3
      
https://github.com/qemu/qemu/commit/72e17a9f86098feb25d2c1f2af043dc5f9f211e3
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic 
instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-6@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5b448f44c92f7355ae2b02af0699d22674cc5f6e
      
https://github.com/qemu/qemu/commit/5b448f44c92f7355ae2b02af0699d22674cc5f6e
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vector floating-point instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-7@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 35f2d795f313c43af5851ca2243317c0b0834c6c
      
https://github.com/qemu/qemu/commit/35f2d795f313c43af5851ca2243317c0b0834c6c
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vector mask instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-8@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: edabcd0e0aea2ac8d68931f31fcf8d3b99a28f20
      
https://github.com/qemu/qemu/commit/edabcd0e0aea2ac8d68931f31fcf8d3b99a28f20
  Author: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Add mask agnostic for vector permutation instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-9@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1ad3f9bdc76c83b23d689a111d5a160c528ac8ba
      
https://github.com/qemu/qemu/commit/1ad3f9bdc76c83b23d689a111d5a160c528ac8ba
  Author: eopXD <eop.chen@sifive.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask 
agnostic behavior

According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".

There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.

This commit adds option 'rvv_ma_all_1s' is added to enable the
behavior, it is default as disabled.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-10@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4696f0ab5c436ed53567ce6baec67c921d9b70ae
      
https://github.com/qemu/qemu/commit/4696f0ab5c436ed53567ce6baec67c921d9b70ae
  Author: Dao Lu <daolu@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.c.inc

  Log Message:
  -----------
  target/riscv: Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.

Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Dao Lu <daolu@rivosinc.com>
Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6934f15b225c9324eafa064d3520a698ed09f9df
      
https://github.com/qemu/qemu/commit/6934f15b225c9324eafa064d3520a698ed09f9df
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/shakti_c.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

The 'fdt' param is not being used in riscv_setup_rom_reset_vec().
Simplify the API by removing it. While we're at it, remove the redundant
'return' statement at the end of function.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Cc: Vijai Kumar K <vijai@behindbytes.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220728181926.2123771-1-danielhb413@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: eacaf440195675bc528f4aac394da7a74a9d95eb
      
https://github.com/qemu/qemu/commit/eacaf440195675bc528f4aac394da7a74a9d95eb
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix priority of csr related check in riscv_csrrw_check

Normally, riscv_csrrw_check is called when executing Zicsr instructions.
And we can only do access control for existed CSRs. So the priority of
CSR related check, from highest to lowest, should be as follows:
1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if not
2) check whether csr is existed: raise RISCV_EXCP_ILLEGAL_INST if not
3) do access control: raise RISCV_EXCP_ILLEGAL_INST or RISCV_EXCP_VIRT_
INSTRUCTION_FAULT if not allowed

The predicates contain parts of function of both 2) and 3), So they need
to be placed in the middle of riscv_csrrw_check

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220803123652.3700-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bf8803c64d756128e4537e22fe86e3717a5274f1
      
https://github.com/qemu/qemu/commit/bf8803c64d756128e4537e22fe86e3717a5274f1
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv: opentitan: bump opentitan version

The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c

Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies which we are currently not supporting in qemu. As of now,
the `boot_rom` has no major significance, however, would be good to
support in the future.

Tested by running utests from the latest tock [1]
(that supports this version of OT).

[1] https://github.com/tock/tock/pull/3056

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 25da6e311336b431d8cf1eaa8fe8688b7ee710ed
      
https://github.com/qemu/qemu/commit/25da6e311336b431d8cf1eaa8fe8688b7ee710ed
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals

Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot
entirely is probably not advisable, but it does at least show signs of
life. Recent Linux kernel versions make use of peripherals that are
missing definitions in QEMU and lead to kernel panics. These issues
almost certain rear their head for other methods of booting, but I was
unable to figure out a suitable HSS version that is recent enough to
support these peripherals & works with QEMU.

With these peripherals added, booting a kernel with the following hangs
hangs waiting for the system controller's hwrng, but the kernel no
longer panics. With the Linux driver for hwrng disabled, it boots to
console.

qemu-system-riscv64 -M microchip-icicle-kit \
        -m 2G -smp 5 \
        -kernel $(vmlinux_bin) \
        -dtb  $(dtb)\
        -initrd $(initramfs) \
        -display none -serial null \
        -serial stdio

More peripherals are added than strictly required to fix the panics in
the hopes of avoiding a replication of this problem in the future.
Some of the peripherals which are in the device tree for recent kernels
are implemented in the FPGA fabric. The eMMC/SD mux, which exists as
an unimplemented device is replaced by a wider entry. This updated
entry covers both the mux & the remainder of the FPGA fabric connected
to the MSS using Fabric Interrconnect (FIC) 3.

Link: 
https://github.com/polarfire-soc/icicle-kit-reference-design#fabric-memory-map
Link: 
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/SupportingCollateral/V1_4_Register_Map.zip
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220813135127.2971754-1-mail@conchuod.ie>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 240b363618bdd981333e8ebbb1cb09e702315b0a
      
https://github.com/qemu/qemu/commit/240b363618bdd981333e8ebbb1cb09e702315b0a
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Remove additional priv version check for mcountinhibit

With .min_priv_version, additiona priv version check is uncessary
for mcountinhibit read/write functions.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220816232321.558250-7-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 53c38f7ab1a5b55d63303d36a42c3e74b5fc9225
      
https://github.com/qemu/qemu/commit/53c38f7ab1a5b55d63303d36a42c3e74b5fc9225
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: fix uart node name

"uart" is not a node name that complies with the dt-schema.
Change the node name to "serial" to ix warnings seen during
dt-validate on a dtbdump of the virt machine such as:
/stuff/qemu/qemu.dtb: uart@10000000: $nodename:0: 'uart@10000000' does not 
match '^serial(@.*)?$'
        From schema: 
/stuff/linux/Documentation/devicetree/bindings/serial/8250.yaml

Reported-by: Rob Herring <robh@kernel.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-id: 20220810184612.157317-2-mail@conchuod.ie
Link: 
https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Fixes: 04331d0b56 ("RISC-V VirtIO Machine")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 95e401d3785a9be9ac4edc7a5a7f9147d917e610
      
https://github.com/qemu/qemu/commit/95e401d3785a9be9ac4edc7a5a7f9147d917e610
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv: virt: fix the plic's address cells

When optional AIA PLIC support was added the to the virt machine, the
address cells property was removed leading the issues with dt-validate
on a dump from the virt machine:
/stuff/qemu/qemu.dtb: plic@c000000: '#address-cells' is a required property
        From schema: 
/stuff/linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Add back the property to suppress the warning.

Reported-by: Rob Herring <robh@kernel.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-id: 20220810184612.157317-3-mail@conchuod.ie
Link: 
https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Fixes: e6faee6585 ("hw/riscv: virt: Add optional AIA APLIC support to virt 
machine")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ae29379998f101aedf32f9168135eb0545257b3c
      
https://github.com/qemu/qemu/commit/ae29379998f101aedf32f9168135eb0545257b3c
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: fix syscon subnode paths

The reset and poweroff features of the syscon were originally added to
top level, which is a valid path for a syscon subnode. Subsequently a
reorganisation was carried out while implementing NUMA in which the
subnodes were moved into the /soc node. As /soc is a "simple-bus", this
path is invalid, and so dt-validate produces the following warnings:

/stuff/qemu/qemu.dtb: soc: poweroff: {'value': [[21845]], 'offset': [[0]], 
'regmap': [[4]], 'compatible': ['syscon-poweroff']} should not be valid under 
{'type': 'object'}
        From schema: 
/home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml
/stuff/qemu/qemu.dtb: soc: reboot: {'value': [[30583]], 'offset': [[0]], 
'regmap': [[4]], 'compatible': ['syscon-reboot']} should not be valid under 
{'type': 'object'}
        From schema: 
/home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml

Move the syscon subnodes back to the top level and silence the warnings.

Reported-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220810184612.157317-4-mail@conchuod.ie
Link: 
https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Fixes: 18df0b4695 ("hw/riscv: virt: Allow creating multiple NUMA sockets")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d1af78745cfc4e8efdda9b3484b32bbb4507276f
      
https://github.com/qemu/qemu/commit/d1af78745cfc4e8efdda9b3484b32bbb4507276f
  Author: Conor Dooley <conor.dooley@microchip.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/core/sysbus-fdt.c

  Log Message:
  -----------
  hw/core: fix platform bus node name

"platform" is not a valid name for a bus node in dt-schema, so warnings
can be see in dt-validate on a dump of the riscv virt dtb:

/stuff/qemu/qemu.dtb: platform@4000000: $nodename:0: 'platform@4000000' does 
not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
        From schema: 
/home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml
"platform-bus" is a valid name, so use that instead.

CC: Rob Herring <robh@kernel.org>
Fixes: 11d306b9df ("hw/arm/sysbus-fdt: helpers for platform bus nodes addition")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-id: 20220810184612.157317-5-mail@conchuod.ie
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e0dea2f55f678a1aa1dab3a25c13f52d68b4ec2b
      
https://github.com/qemu/qemu/commit/e0dea2f55f678a1aa1dab3a25c13f52d68b4ec2b
  Author: Rahul Pathak <rpathak@ventanamicro.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Add xicondops in ISA entry

XVentanaCondOps is Ventana custom extension. Add
its extension entry in the ISA Ext array

Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220816045408.1231135-1-rpathak@ventanamicro.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dc9acc9ce4add37bc5b4437ae9117c318b4f09d4
      
https://github.com/qemu/qemu/commit/dc9acc9ce4add37bc5b4437ae9117c318b4f09d4
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/intc/riscv_imsic.c
    M hw/riscv/virt.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Use official extension names for AIA CSRs

The arch review of AIA spec is completed and we now have official
extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
AIA CSRs).

Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf)

Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
   which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220820042958.377018-1-apatel@ventanamicro.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7cbcc538f4b3040db1e39a6547efa501a8a44907
      
https://github.com/qemu/qemu/commit/7cbcc538f4b3040db1e39a6547efa501a8a44907
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/intc/riscv_aclint.c
    M hw/timer/ibex_timer.c
    M include/hw/intc/riscv_aclint.h
    M include/hw/timer/ibex_timer.h
    M target/riscv/cpu.h
    M target/riscv/machine.c

  Log Message:
  -----------
  hw/intc: Move mtimer/mtimecmp to aclint

Historically, The mtime/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.

Move them to the ACLINT device. This also emulates the real hardware
more closely.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 43888c2f1823212b1064a6a94d65d8acaf954478
      
https://github.com/qemu/qemu/commit/43888c2f1823212b1064a6a94d65d8acaf954478
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/machine.c
    M target/riscv/meson.build
    A target/riscv/time_helper.c
    A target/riscv/time_helper.h

  Log Message:
  -----------
  target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3ec0fe18a31fabfe999b480e4c21847ac0d51560
      
https://github.com/qemu/qemu/commit/3ec0fe18a31fabfe999b480e4c21847ac0d51560
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/machine.c
    M target/riscv/time_helper.c

  Log Message:
  -----------
  target/riscv: Add vstimecmp support

vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 14664483457b21235be42fbfb534e5ea881508b8
      
https://github.com/qemu/qemu/commit/14664483457b21235be42fbfb534e5ea881508b8
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/machine.c
    M target/riscv/pmu.c
    M target/riscv/pmu.h

  Log Message:
  -----------
  target/riscv: Add sscofpmf extension support

The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension. As the extension doesn't have any
provision for the overflow bit for fixed counters, the fixed events
can also be monitoring using programmable counters. The underlying
counters for cycle and instruction counters are always running. Thus,
a separate timer device is programmed to handle the overflow.

Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ade445ef85aa0cf711a311132cb458f11f6a6d12
      
https://github.com/qemu/qemu/commit/ade445ef85aa0cf711a311132cb458f11f6a6d12
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Simplify counter predicate function

All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.

Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 892320facd73136b48bb58af3bd742686eb05416
      
https://github.com/qemu/qemu/commit/892320facd73136b48bb58af3bd742686eb05416
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Add few cache related PMU events

Qemu can monitor the following cache related PMU events through
tlb_fill functions.

1. DTLB load/store miss
3. ITLB prefetch miss

Increment the PMU counter in tlb_fill function.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: abd9a20665496aa4f3680fbbd42b5c389ea53d1c
      
https://github.com/qemu/qemu/commit/abd9a20665496aa4f3680fbbd42b5c389ea53d1c
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M hw/riscv/virt.c
    M target/riscv/pmu.c
    M target/riscv/pmu.h

  Log Message:
  -----------
  hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.

Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-5-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f0551560b5c01b1dcbed1ac46ca0bd1155330f5f
      
https://github.com/qemu/qemu/commit/f0551560b5c01b1dcbed1ac46ca0bd1155330f5f
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e46e2628e9fcce39e7ae28ac8c24bcc643ac48eb
      
https://github.com/qemu/qemu/commit/e46e2628e9fcce39e7ae28ac8c24bcc643ac48eb
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-09-07 (Wed, 07 Sep 2022)

  Changed paths:
    M disas/riscv.c
    M docs/about/build-platforms.rst
    M hw/core/sysbus-fdt.c
    M hw/intc/riscv_aclint.c
    M hw/intc/riscv_imsic.c
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/shakti_c.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M hw/timer/ibex_timer.c
    M include/hw/intc/riscv_aclint.h
    M include/hw/riscv/boot.h
    M include/hw/riscv/microchip_pfsoc.h
    M include/hw/riscv/opentitan.h
    M include/hw/riscv/virt.h
    M include/hw/timer/ibex_timer.h
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M roms/opensbi
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn16.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/instmap.h
    M target/riscv/internals.h
    M target/riscv/machine.c
    M target/riscv/meson.build
    M target/riscv/pmu.c
    M target/riscv/pmu.h
    A target/riscv/time_helper.c
    A target/riscv/time_helper.h
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20220907' of 
https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 7.2

* Update [m|h]tinst CSR in interrupt handling
* Force disable extensions if priv spec version does not match
* fix shifts shamt value for rv128c
* move zmmul out of the experimental
* virt: pass random seed to fdt
* Add checks for supported extension combinations
* Upgrade OpenSBI to v1.1
* Fix typo and restore Pointer Masking functionality for RISC-V
* Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension
* Add Zihintpause support
* opentitan: bump opentitan version
* microchip_pfsoc: fix kernel panics due to missing peripherals
* Remove additional priv version check for mcountinhibit
* virt machine device tree improvements
* Add xicondops in ISA entry
* Use official extension names for AIA CSRs

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmMYUCUACgkQIeENKd+X
# cFRpEQf/T1FFcGq3TZrEPmqMdFPUSb+SEJNgwYFfloqkNjB2HIFbd2tKWAE1Tgjr
# esV00p7YPyox1Ct+fKdwSxDxRSN9OI56v+nI8ZFwluVu7vpChuTFmOHur8rNxl1T
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# 1gdv5ZF5BXDJsGs7xHvE92dRzQEVN+As64IjlknFHHpmCM1b+Ah3GekXUbKmBuDG
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# fXrnML+MQFUKZ03AZ9lWvxcu7kXfWA==
# =7mGD
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 07 Sep 2022 04:02:45 EDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220907' of https://github.com/alistair23/qemu: (44 
commits)
  target/riscv: Update the privilege field for sscofpmf CSRs
  hw/riscv: virt: Add PMU DT node to the device tree
  target/riscv: Add few cache related PMU events
  target/riscv: Simplify counter predicate function
  target/riscv: Add sscofpmf extension support
  target/riscv: Add vstimecmp support
  target/riscv: Add stimecmp support
  hw/intc: Move mtimer/mtimecmp to aclint
  target/riscv: Use official extension names for AIA CSRs
  target/riscv: Add xicondops in ISA entry
  hw/core: fix platform bus node name
  hw/riscv: virt: fix syscon subnode paths
  hw/riscv: virt: fix the plic's address cells
  hw/riscv: virt: fix uart node name
  target/riscv: Remove additional priv version check for mcountinhibit
  hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals
  hw/riscv: opentitan: bump opentitan version
  target/riscv: Fix priority of csr related check in riscv_csrrw_check
  hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()
  target/riscv: Add Zihintpause support
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/946e9bccf12f...e46e2628e9fc



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