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[Qemu-commits] [qemu/qemu] c49b67: pseries: Update SLOF firmware image
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-commits] [qemu/qemu] c49b67: pseries: Update SLOF firmware image |
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Date: |
Thu, 01 Sep 2022 13:26:33 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c49b67f72b1a875ca355a170759303b0faa959ca
https://github.com/qemu/qemu/commit/c49b67f72b1a875ca355a170759303b0faa959ca
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2022-08-30 (Tue, 30 Aug 2022)
Changed paths:
M docs/system/ppc/pseries.rst
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
The only change is that now SLOF can also boot big endian zImage
but kernel-addr=0 is still required.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 21d3a78ed9cf470f87180db62f7aa1296b7b0ee5
https://github.com/qemu/qemu/commit/21d3a78ed9cf470f87180db62f7aa1296b7b0ee5
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2022-08-30 (Tue, 30 Aug 2022)
Changed paths:
M hw/ppc/pnv.c
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/machine.c
Log Message:
-----------
target/ppc: Fix host PVR matching for KVM
ppc_cpu_compare_class_pvr_mask() should match the best CPU class in the
family, because it is used by the KVM subsystem to find the host CPU
class. Since commit 03ae4133ab8 ("target-ppc: Add pvr_match()
callback"), it matches any class in the family (the first one in the
comparison list).
Since commit f30c843ced5 ("ppc/pnv: Introduce PowerNV machines with
fixed CPU models"), pnv has relied on pnv_match having these new
semantics to check machine compatibility with a CPU family.
Resolve this by adding a parameter to the pvr_match function to select
the best or any match, and restore the old behaviour for the KVM case.
Prior to this fix, e.g., a POWER9 DD2.3 KVM host matches to the
power9_v1.0 class (because that happens to be the first POWER9 family
CPU compared). After the patch, it matches the power9_v2.0 class.
This approach requires pnv_match contain knowledge of the CPU classes
implemented in the same family, which feels ugly. But pushing the 'best'
match down to the class would still require they know about one another
which is not obviously much better. For now this gets things working.
Fixes: 03ae4133ab8 ("target-ppc: Add pvr_match() callback")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220731013358.170187-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0bf4d77e5922128506a3495d72ee9f432726c085
https://github.com/qemu/qemu/commit/0bf4d77e5922128506a3495d72ee9f432726c085
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/meson.build
M hw/ppc/pnv.c
A hw/ppc/pnv_sbe.c
M hw/ppc/pnv_xscom.c
M hw/ppc/trace-events
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_sbe.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Add initial P9/10 SBE model
The SBE (Self Boot Engine) are on-chip microcontrollers that perform
early boot steps, as well as provide some runtime facilities (e.g.,
timer, secure register access, MPIPL). The latter facilities are
accessed mostly via a message system called SBEFIFO.
This driver provides initial emulation for the SBE runtime registers
and a very basic SBEFIFO implementation that provides the timer
command. This covers the basic SBE behaviour expected by skiboot when
booting.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220811093726.1442343-1-npiggin@gmail.com>
[danielhb: fixed SBE_HOST_RESPONSE_MASK long line]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c40da5c6fb6dd243e906900de1d22cf20e32a8cd
https://github.com/qemu/qemu/commit/c40da5c6fb6dd243e906900de1d22cf20e32a8cd
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-types.h
Log Message:
-----------
fpu: Add rebias bool, value and operation
Added the possibility of recalculating a result if it overflows or
underflows, if the result overflow and the rebias bool is true then the
intermediate result should have 3/4 of the total range subtracted from
the exponent. The same for underflow but it should be added to the
exponent of the intermediate number instead.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220805141522.412864-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 08e185cadb24b038574dad676d4dae8488ba8b6e
https://github.com/qemu/qemu/commit/08e185cadb24b038574dad676d4dae8488ba8b6e
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M target/ppc/cpu.c
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Bugfix FP when OE/UE are set
When an overflow exception occurs and OE is set the intermediate result
should be adjusted (by subtracting from the exponent) to avoid rounding
to inf. The same applies to an underflow exceptionion and UE (but adding
to the exponent). To do this set the fp_status.rebias_overflow when OE
is set and fp_status.rebias_underflow when UE is set as the FPU will
recalculate in case of a overflow/underflow if the according rebias* is
set.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220805141522.412864-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 91bcee7157b0a1c627705d5a24076a3058ea01a7
https://github.com/qemu/qemu/commit/91bcee7157b0a1c627705d5a24076a3058ea01a7
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
M include/hw/pci-host/pnv_phb3.h
Log Message:
-----------
ppc/pnv: add PHB3 bus init helper
The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
regions, registering it via pci_register_root_bus() and then setup the
iommu.
We'll want to init the bus from outside pnv_phb3.c when the bus is
removed from the PnvPHB3 device and put into a new parent PnvPHB device.
The new pnv_phb3_bus_init() helper will be used by the parent to init
the bus when using the PHB3 backend.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-2-danielhb413@gmail.com>
Commit: e4e6db5283f775e44879246c6c93cb2462cf742f
https://github.com/qemu/qemu/commit/e4e6db5283f775e44879246c6c93cb2462cf742f
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/meson.build
A hw/pci-host/pnv_phb.c
A hw/pci-host/pnv_phb.h
Log Message:
-----------
ppc/pnv: add PnvPHB base/proxy device
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' pointer that will be initialized
with the PHB implementation that the device is going to use.
The initialization of the PHB backend is done by checking the PHB
version via a 'version' attribute that can be set via a global machine
property. The 'version' field will be used to make adjustments based on
the running version, e.g. PHB3 uses a 'chip' reference while PHB4 uses
'pec'. To init the PnvPHB bus we'll rely on helpers for each version.
The version 3 helper is already added (pnv_phb3_bus_init), the PHB4
helper will be added later on.
For now let's add the basic logic of the PnvPHB object, which consists
mostly of pnv_phb_realize() doing all the work of checking the
phb->version set, initializing the proper backend, passing through its
attributes to the chosen backend, finalizing the backend realize and
adding a root port in the end.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-3-danielhb413@gmail.com>
Commit: 1f5d6b2ad14df9daad17e81d9e247bd1fd2fd5fc
https://github.com/qemu/qemu/commit/1f5d6b2ad14df9daad17e81d9e247bd1fd2fd5fc
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb3.h
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: turn PnvPHB3 into a PnvPHB backend
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a
couple of instances in pnv_phb3.c that needs to access the PCI bus, so a
phb_base pointer is added to allow access to the parent PnvPHB. The
PnvPHB3 root port will now be connected to a PnvPHB object.
In pnv.c, the powernv8 machine chip8 will now hold an array of PnvPHB
objects. pnv_get_phb3_child() needs to be adapted to return the PnvPHB3
backend from the PnvPHB child. A global property is added in
pnv_machine_power8_class_init() to ensure that all PnvPHBs are created
with phb->version = 3.
After all these changes we're still able to boot a powernv8 machine with
default settings. The real gain will come with user created PnvPHB
devices, coming up next.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-4-danielhb413@gmail.com>
Commit: fe5bfd4bb816faa1b3fa8c3c23165cdbadfa5c91
https://github.com/qemu/qemu/commit/fe5bfd4bb816faa1b3fa8c3c23165cdbadfa5c91
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/pci-host/pnv_phb4.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: add PHB4 bus init helper
Similar to what we already did for the PnvPHB3 device, let's add a
helper to init the bus when using a PnvPHB4. This helper will be used by
PnvPHb when PnvPHB4 turns into a backend.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-5-danielhb413@gmail.com>
Commit: 210aacb3b92707ecc5de811c743322ca395c0fa6
https://github.com/qemu/qemu/commit/210aacb3b92707ecc5de811c743322ca395c0fa6
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: turn PnvPHB4 into a PnvPHB backend
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.
pnv_phb4_pec now creates a PnvPHB object.
The powernv9 machine class will create PnvPHB devices with version '4'.
powernv10 will create using version '5'. Both are using global machine
properties in their class_init() to do that.
These changes will benefit us when adding PnvPHB user creatable devices
for powernv9 and powernv10.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-6-danielhb413@gmail.com>
Commit: 5ba76b61a2d3c90daa264bbaa14464eb3c49caa9
https://github.com/qemu/qemu/commit/5ba76b61a2d3c90daa264bbaa14464eb3c49caa9
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/pci-host/pnv_phb.h
Log Message:
-----------
ppc/pnv: add pnv-phb-root-port device
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is that
pnv-phb4-root-port has the pnv_phb4_root_port_reset() callback. All
other differences can be merged in a single device without too much
trouble.
This patch introduces the unified pnv-phb-root-port that, in time, will
be used as the default root port for the pnv-phb device.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-7-danielhb413@gmail.com>
Commit: 805150619e47eea910c760e1fde8d3e7e61a3a24
https://github.com/qemu/qemu/commit/805150619e47eea910c760e1fde8d3e7e61a3a24
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/pci-host/pnv_phb3.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb3.h
Log Message:
-----------
ppc/pnv: remove pnv-phb3-root-port
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-8-danielhb413@gmail.com>
Commit: c8d14603e998ee41313e989cec590c3ec8ddc923
https://github.com/qemu/qemu/commit/c8d14603e998ee41313e989cec590c3ec8ddc923
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: remove pnv-phb4-root-port
The unified pnv-phb-root-port can be used instead. The phb4-root-port
device isn't exposed to the user in any official QEMU release so there's
no ABI breakage in removing it.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-9-danielhb413@gmail.com>
Commit: 17c681e92ddd66b8a5c425ea6a1c6ec3a4e079d4
https://github.com/qemu/qemu/commit/17c681e92ddd66b8a5c425ea6a1c6ec3a4e079d4
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: remove root port name from pnv_phb_attach_root_port()
We support only a single root port, PNV_PHB_ROOT_PORT.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-10-danielhb413@gmail.com>
Commit: cb6a5c26446f797252a479f456da030dc7febb20
https://github.com/qemu/qemu/commit/cb6a5c26446f797252a479f456da030dc7febb20
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: remove pecc->rp_model
The attribute is unused.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-11-danielhb413@gmail.com>
Commit: d69db7dadfe7fd13731a9621520ffb2f382f1675
https://github.com/qemu/qemu/commit/d69db7dadfe7fd13731a9621520ffb2f382f1675
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: remove PnvPHB4.version
It's unused.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-12-danielhb413@gmail.com>
Commit: e5ea94360eba4818467283a259d8d681f0da799f
https://github.com/qemu/qemu/commit/e5ea94360eba4818467283a259d8d681f0da799f
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: move attach_root_port helper to pnv-phb.c
The helper is only used in this file.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-13-danielhb413@gmail.com>
Commit: 8ec1e4f1ef974e901b416fef6c3b38a5cc2eeffa
https://github.com/qemu/qemu/commit/8ec1e4f1ef974e901b416fef6c3b38a5cc2eeffa
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
M include/hw/pci-host/pnv_phb3.h
Log Message:
-----------
ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties
We rely on the phb-id and chip-id, which are PHB properties, to assign
chassis and slot to the root port. For default devices this is no big
deal: the root port is being created under pnv_phb_realize() and the
values are being passed on via the 'index' and 'chip-id' of the
pnv_phb_attach_root_port() helper.
If we want to implement user created root ports we have a problem. The
user created root port will not be aware of which PHB it belongs to,
unless we're willing to violate QOM best practices and access the PHB
via dev->parent_bus->parent. What we can do is to access the root bus
parent bus.
Since we're already assigning the root port as QOM child of the bus, and
the bus is initiated using PHB properties, let's add phb-id and chip-id
as properties of the bus. This will allow us trivial access to them, for
both user-created and default root ports, without doing anything too
shady with QOM.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-2-danielhb413@gmail.com>
Commit: b7c1750dc440bb46ddc38dd0c391d6394db7bdb1
https://github.com/qemu/qemu/commit/b7c1750dc440bb46ddc38dd0c391d6394db7bdb1
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb4.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofold:
- there's not user side advantage in doing so. Unifying the root ports
presents a clear user QOL change when we enable user created devices back.
The buses objects, aside from having a different QOM name, is transparent
to the user;
- we leave a door opened in case we want to increase the root port limit
for phb4/5 later on without having to deal with phb3 code.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-3-danielhb413@gmail.com>
Commit: c2f3f78af5fd664f95748ebc918ae86463690249
https://github.com/qemu/qemu/commit/c2f3f78af5fd664f95748ebc918ae86463690249
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
Log Message:
-----------
ppc/pnv: set root port chassis and slot using Bus properties
For default root ports we have a way of accessing chassis and slot,
before root_port_realize(), via pnv_phb_attach_root_port(). For the
future user created root ports this won't be the case: we can't use
this helper because we don't have access to the PHB phb-id/chip-id
values.
In earlier patches we've added phb-id and chip-id to pnv-phb-root-bus
objects. We're now able to use the bus to retrieve them. The bus is
reachable for both user created and default devices, so we're changing
all the code paths. This also allow us to validate these changes with
the existing default devices.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-4-danielhb413@gmail.com>
Commit: ba47c3a4f888e99dedde1fed740927e973f9bc32
https://github.com/qemu/qemu/commit/ba47c3a4f888e99dedde1fed740927e973f9bc32
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add helpers for pnv-phb user devices
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-phbs, matching them with default
pnv-phbs.
A new helper pnv_phb_user_device_init() is created to handle
user-created devices setup. We're going to call it inside
pnv_phb_realize() in case we're realizing an user created device. This
will centralize all user device realated in a single spot, leaving the
realize functions of the phb3/phb4 backends untouched.
Another helper called pnv_chip_add_phb() was added to handle the
particularities of each chip version when adding a new PHB.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-5-danielhb413@gmail.com>
Commit: 0d512c7120a2638da242436d45bd8a82ffffe27a
https://github.com/qemu/qemu/commit/0d512c7120a2638da242436d45bd8a82ffffe27a
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: turn chip8->phbs[] into a PnvPHB* array
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is assigned during pnv_chip_power8_realize(),
while the user created needs to search which chip it belongs to.
Aside from that there shouldn't be any difference. Making the default
PHBs behave in line with the user created ones will make it easier to
re-introduce them later on. It will also make the code easier to follow
since we are dealing with them in equal manner.
The first step is to turn chip8->phbs[] into a PnvPHB3 pointer array.
This will allow us to assign user created PHBs into it later on. The way
we initilize the default case is now more in line with that would happen
with the user created case: the object is created, parented by the chip
because pnv_xscom_dt() relies on it, and then assigned to the array.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-6-danielhb413@gmail.com>
Commit: 892c3ad0d5d6bb9b1e414d61118e93362ecab782
https://github.com/qemu/qemu/commit/892c3ad0d5d6bb9b1e414d61118e93362ecab782
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: enable user created pnv-phb for powernv8
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-7-danielhb413@gmail.com>
Commit: c1471772772499b36659a0785d9a3de759d5aee2
https://github.com/qemu/qemu/commit/c1471772772499b36659a0785d9a3de759d5aee2
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: add PHB4 helpers for user created pnv-phb
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that was
reverted by commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5}
devices". We'll use it to determine the appropriate PEC for a given user
created pnv-phb that uses a PHB4 backend.
This is done during realize() time, in pnv_phb_user_device_init().
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-8-danielhb413@gmail.com>
Commit: d786be3fe7466ff96db96b86e6fee437136d63d7
https://github.com/qemu/qemu/commit/d786be3fe7466ff96db96b86e6fee437136d63d7
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: enable user created pnv-phb for powernv9
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-9-danielhb413@gmail.com>
Commit: 607e9316d3bd64ea6c1f7193ff9a7085a272244e
https://github.com/qemu/qemu/commit/607e9316d3bd64ea6c1f7193ff9a7085a272244e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-10-danielhb413@gmail.com>
Commit: f1327fde3556aeea17f721f4fa2bb8bcf13b2038
https://github.com/qemu/qemu/commit/f1327fde3556aeea17f721f4fa2bb8bcf13b2038
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: user creatable pnv-phb for powernv10
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220811163950.578927-11-danielhb413@gmail.com>
Commit: 3466bb50ec7c49a63b4a146c82d4030742451f40
https://github.com/qemu/qemu/commit/3466bb50ec7c49a63b4a146c82d4030742451f40
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
Log Message:
-----------
ppc/pnv: consolidate pnv_parent_*_fixup() helpers
We have 2 helpers that amends the QOM and parent bus of a given object,
repectively. These 2 helpers are called together, and not by accident.
Due to QOM internals, doing an object_unparent() will result in the
device being removed from its parent bus. This means that changing the
QOM parent requires reassigning the parent bus again.
Create a single helper called pnv_parent_fixup(), documenting some of
the QOM specifics that we're dealing with the unparenting/parenting
mechanics, and handle both the QOM and the parent bus assignment.
Next patch will make use of this function to handle a case where we need
to change the QOM parent while keeping the same parent bus assigned
beforehand.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220819094748.400578-2-danielhb413@gmail.com>
Commit: 6a1e1ce2efb9c22723f9f7cada5d5a31842eb37d
https://github.com/qemu/qemu/commit/6a1e1ce2efb9c22723f9f7cada5d5a31842eb37d
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/pci-host/pnv_phb.c
Log Message:
-----------
ppc/pnv: fix QOM parenting of user creatable root ports
User creatable root ports are being parented by the 'peripheral' or the
'peripheral-anon' container. This happens because this is the regular
QOM schema for sysbus devices that are added via the command line.
Let's make this QOM hierarchy similar to what we have with default root
ports, i.e. the root port must be parented by the pnv-root-bus. To do
that we change the qom and bus parent of the root port during
root_port_realize(). The realize() is shared by the default root port
code path, so we can remove the code inside pnv_phb_attach_root_port()
that was adding the root port as a child of the bus as well.
After all that, remove pnv_phb_attach_root_port() and create the root
port explictly in the 'default_enabled()' case of pnv_phb_realize().
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220819094748.400578-3-danielhb413@gmail.com>
Commit: 1335caf312a9522fe3abe6231891456ada721de2
https://github.com/qemu/qemu/commit/1335caf312a9522fe3abe6231891456ada721de2
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M MAINTAINERS
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M docs/system/ppc/embedded.rst
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Remove taihu machine
It has been deprecated since 7.0.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220809153904.485018-2-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e67b374d0806d75b33bd4bf0fd6c0d6d7cd5e913
https://github.com/qemu/qemu/commit/e67b374d0806d75b33bd4bf0fd6c0d6d7cd5e913
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Introduce a PPC405 generic machine
We will use this machine as a base to define the ref405ep and possibly
the PPC405 hotfoot board as found in the Linux kernel.
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220809153904.485018-3-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 041816c6d5e72896f3e829e8be6a80969c6cf047
https://github.com/qemu/qemu/commit/041816c6d5e72896f3e829e8be6a80969c6cf047
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Move devices under the ref405ep machine
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220809153904.485018-4-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: df2372086f8af030bf5c2d1e1a46812d59923b80
https://github.com/qemu/qemu/commit/df2372086f8af030bf5c2d1e1a46812d59923b80
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Move SRAM under the ref405ep machine
It doesn't belong to the generic machine nor the SoC. Fix a typo in
the name while we are at it.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220809153904.485018-5-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3b758ca2f05fccd73b49cf88eff7d2dbf489902e
https://github.com/qemu/qemu/commit/3b758ca2f05fccd73b49cf88eff7d2dbf489902e
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Introduce a PPC405 SoC
It is an initial model to start QOMification of the PPC405 board.
QOM'ified devices will be reintroduced one by one. Start with the
memory regions, which name prefix is changed to "ppc405".
Also, initialize only one RAM bank. The second bank is a dummy one
(zero size) which is here to match the hard coded number of banks in
ppc405ep_init().
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220809153904.485018-6-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5b0f170a8aa2b83d04aa6769eef35013a24ac52f
https://github.com/qemu/qemu/commit/5b0f170a8aa2b83d04aa6769eef35013a24ac52f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Start QOMification of the SoC
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize(). We can also adjust the number of banks now
that we have control on ppc4xx_sdram_init().
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220809153904.485018-7-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b42ad437562f72b31e5743db4ddf183a8e810eb2
https://github.com/qemu/qemu/commit/b42ad437562f72b31e5743db4ddf183a8e810eb2
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc/ppc405: QOM'ify CPU
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in the SoC realize routine. We will clean that up in the
following patches.
ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
this could be done in model initializer of the CPU families needing it.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220809153904.485018-8-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 629cae617039e03d5bfdc0120ade69135a009d33
https://github.com/qemu/qemu/commit/629cae617039e03d5bfdc0120ade69135a009d33
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc/ppc4xx: Introduce a DCR device model
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model these accesses with a DCR namespace and DCR
memory regions but today the DCR handlers are installed in a DCR table
under the CPU. Instead, introduce a little device model wrapper to hold
a CPU link and handle registration of DCR handlers.
The DCR device inherits from SysBus because most of these devices also
have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
to install the device model in the overall SoC.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: Explicit opaque parameter for dcr callbacks]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<9b21bdf55e0a728f093bad299e030d98f302ded0.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4a7d2b7e5cebd00bdcc842517174ad33fd4934cb
https://github.com/qemu/qemu/commit/4a7d2b7e5cebd00bdcc842517174ad33fd4934cb
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: QOM'ify CPC
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<23393cb91a2c6c560a4461b3e9d1baa48ae28f74.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 269fbb5b8ac0506b872ad3df277f23de1856ed15
https://github.com/qemu/qemu/commit/269fbb5b8ac0506b872ad3df277f23de1856ed15
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc/ppc405: QOM'ify GPT
The GPT controller is currently modeled as a SysBus device with a
unique memory region, a couple of IRQs and a timer.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<8950ab26e78173f94ba65bc61bcfd0631de1fe61.1660746880.git.balaton@eik.bme.hu>
[danielhb: check if timer != NULL in ppc405_gpt_finalize()]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2847eb40891b252e66a178532d26a8f7f91c735e
https://github.com/qemu/qemu/commit/2847eb40891b252e66a178532d26a8f7f91c735e
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: QOM'ify OCM
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<ecb93d2d5993bb7a970365744c7d342d4abcb017.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 125277c6a88d93760c2ec28c74bf3a1c30b90113
https://github.com/qemu/qemu/commit/125277c6a88d93760c2ec28c74bf3a1c30b90113
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc/ppc405: QOM'ify GPIO
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<e95d7849f3768e1f9a2846c4b282392750678b3e.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 82c86e304ad9532308486c516fe9396658a72d72
https://github.com/qemu/qemu/commit/82c86e304ad9532308486c516fe9396658a72d72
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: QOM'ify DMA
The DMA controller is currently modeled as a DCR device with a couple
of IRQs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<4738b3c7cf18c328f05aaaddc555a46219431335.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 415a6333d44818b6ae23d4dda813fa8a8f0df2fc
https://github.com/qemu/qemu/commit/415a6333d44818b6ae23d4dda813fa8a8f0df2fc
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/sam460ex.c
Log Message:
-----------
ppc/ppc405: QOM'ify EBC
EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<51a0769ab605c5158f4f2f1c896725d5fe7a073b.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 72beecc20c72fefb97bc4a4e558ba4e884166629
https://github.com/qemu/qemu/commit/72beecc20c72fefb97bc4a4e558ba4e884166629
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc/ppc405: QOM'ify OPBA
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<38476bc43d2332db2f09dbede9eff5234d6ce217.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2841430e6ae5cee6e58b1f0d86b77c6bbbc8c2d3
https://github.com/qemu/qemu/commit/2841430e6ae5cee6e58b1f0d86b77c6bbbc8c2d3
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: QOM'ify POB
POB is currently modeled as a simple DCR device.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<2bb1a89182523059ecb0e8d20c22a293534dec17.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 695bce07dc1c0f7de054fb471a494d572e649e07
https://github.com/qemu/qemu/commit/695bce07dc1c0f7de054fb471a494d572e649e07
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/sam460ex.c
Log Message:
-----------
ppc/ppc405: QOM'ify PLB
PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<c4256d1bffca86fe1d696aa9c56732e5f563e114.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: da116a8aab47695a8364708f2e1d14ed6fcc659f
https://github.com/qemu/qemu/commit/da116a8aab47695a8364708f2e1d14ed6fcc659f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc/ppc405: QOM'ify MAL
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<d54a243dff94d95ba30dbcc09c27700a90ade932.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2d54aaf121d7a94a57b05059b15e9cbe670734a2
https://github.com/qemu/qemu/commit/2d54aaf121d7a94a57b05059b15e9cbe670734a2
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx: Move PLB model to ppc4xx_devs.c
The PLB is shared between 405 and 440 so move it to the shared file.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<2498384bf3e18959ee8cb984d72fb66b8a6ecadc.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 052c779b4c2c08e07b77046e9acfbe30de2c3562
https://github.com/qemu/qemu/commit/052c779b4c2c08e07b77046e9acfbe30de2c3562
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx: Rename ppc405-plb to ppc4xx-plb
This device is shared between different 4xx socs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<5b13ebfd12a71a28035bed5a915cbeee81cf21d1.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 127ba8d03e270fcbb5d71ea7a90609680803027d
https://github.com/qemu/qemu/commit/127ba8d03e270fcbb5d71ea7a90609680803027d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx: Move EBC model to ppc4xx_devs.c
The EBC is shared between 405 and 440 so move it to shared file.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<10eae70509ca4bd74858fc2c0a0f0e4eb9330199.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: cba58aa7629b94d6938dcac1fd5443f51daee2c9
https://github.com/qemu/qemu/commit/cba58aa7629b94d6938dcac1fd5443f51daee2c9
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx: Rename ppc405-ebc to ppc4xx-ebc
This device is shared between different 4xx socs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<63d9b14c8ff5f73e35bffca1036394b5235735ee.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e9d20f37175bc89d8bca37304404f118918a9911
https://github.com/qemu/qemu/commit/e9d20f37175bc89d8bca37304404f118918a9911
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Use an embedded PPCUIC model in SoC state
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<ac5f010f4eb3ade061c65bc39a049f231f75574a.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a55b213646d8a62515912490d259cf84d2f9e168
https://github.com/qemu/qemu/commit/a55b213646d8a62515912490d259cf84d2f9e168
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/intc/ppc-uic.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/sam460ex.c
M hw/ppc/virtex_ml507.c
M include/hw/intc/ppc-uic.h
Log Message:
-----------
hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device
Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu
link and make it uniform with the other PPC4xx devices.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<eb548130cf60aea8a6ea4dba4dee1686b3cabc3d.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 111913fb2da19cb72e208a951b11f897f65cc8c7
https://github.com/qemu/qemu/commit/111913fb2da19cb72e208a951b11f897f65cc8c7
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Use an explicit I2C object
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus from the machine init routine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: Symplify sysbus device casts for readibility]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<68eb8b5ac408ca8cc981ebf53a3e154c0d34c7f6.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ea9b3186954ff07efbaad771e4c5674518fe872f
https://github.com/qemu/qemu/commit/ea9b3186954ff07efbaad771e4c5674518fe872f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: QOM'ify FPGA
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<ed6ff1705dadb46b456e424aa0f0420f1d18d92c.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b5aae5f66098655f44cbacf463e358605e380889
https://github.com/qemu/qemu/commit/b5aae5f66098655f44cbacf463e358605e380889
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc405: Move machine specific code to ppc405_boards.c
These are only used by the board code so move out from the shared SoC
model and put it in the boards file.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<2b23bcaaf191f96b217cbd06a6038694024862c3.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: adb566d371141d403a8e55b8728d7ab20389d248
https://github.com/qemu/qemu/commit/adb566d371141d403a8e55b8728d7ab20389d248
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/Kconfig
M hw/ppc/sam460ex.c
Log Message:
-----------
hw/ppc/sam460ex: Remove PPC405 dependency from sam460ex
Now that shared PPC4xx devices are separated from PPC405 ones we can
drop this depencency.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<cf6c1d280f830beeea41128595c8c026d5126d2b.1660762465.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 56a5b199e4dd3043eb8f0954bdd71988f063366a
https://github.com/qemu/qemu/commit/56a5b199e4dd3043eb8f0954bdd71988f063366a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/Kconfig
Log Message:
-----------
hw/ppc/Kconfig: Move imply before select
In pegasos2 section move imply before select to match other sections.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<4d46dde64c2e5df6db3f92426fb3ae885939c2b0.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1b46bc17f49a48c8156a82bb8b66b716d1d45d00
https://github.com/qemu/qemu/commit/1b46bc17f49a48c8156a82bb8b66b716d1d45d00
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc4xx_devs.c
Log Message:
-----------
ppc/ppc4xx: Fix sdram trace events
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<0a3e454eb7fd5f2b807a9c752c28693f27829f1d.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 95e22932870f523765910b01c2dc5b845b8bec85
https://github.com/qemu/qemu/commit/95e22932870f523765910b01c2dc5b845b8bec85
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-08-31 (Wed, 31 Aug 2022)
Changed paths:
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_pci.c
Log Message:
-----------
ppc4xx: Fix code style problems reported by checkpatch
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<62798fbe9c200da3e0c870601ed9162b1c3a50a5.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 7dd9d7e0bd29abf590d1ac235c0a00606ef81153
https://github.com/qemu/qemu/commit/7dd9d7e0bd29abf590d1ac235c0a00606ef81153
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-09-01 (Thu, 01 Sep 2022)
Changed paths:
M MAINTAINERS
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M docs/system/ppc/embedded.rst
M docs/system/ppc/pseries.rst
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M hw/intc/ppc-uic.c
M hw/pci-host/meson.build
A hw/pci-host/pnv_phb.c
A hw/pci-host/pnv_phb.h
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/Kconfig
M hw/ppc/meson.build
M hw/ppc/pnv.c
A hw/ppc/pnv_sbe.c
M hw/ppc/pnv_xscom.c
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_pci.c
M hw/ppc/sam460ex.c
M hw/ppc/trace-events
M hw/ppc/virtex_ml507.c
M include/fpu/softfloat-types.h
M include/hw/intc/ppc-uic.h
M include/hw/pci-host/pnv_phb3.h
M include/hw/pci-host/pnv_phb4.h
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_sbe.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/ppc4xx.h
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
M target/ppc/cpu-qom.h
M target/ppc/cpu.c
M target/ppc/cpu_init.c
M target/ppc/fpu_helper.c
M target/ppc/machine.c
Log Message:
-----------
Merge tag 'pull-ppc-20220831' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-08-31:
In the first 7.2 queue we have changes in the powernv pnv-phb handling,
the start of the QOMification of the ppc405 model, the removal of the
taihu machine, a new SLOF image and others.
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# gpg: Signature made Wed 31 Aug 2022 16:09:58 EDT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20220831' of https://gitlab.com/danielhb/qemu: (60 commits)
ppc4xx: Fix code style problems reported by checkpatch
ppc/ppc4xx: Fix sdram trace events
hw/ppc/Kconfig: Move imply before select
hw/ppc/sam460ex: Remove PPC405 dependency from sam460ex
ppc405: Move machine specific code to ppc405_boards.c
ppc/ppc405: QOM'ify FPGA
ppc/ppc405: Use an explicit I2C object
hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device
ppc/ppc405: Use an embedded PPCUIC model in SoC state
ppc4xx: Rename ppc405-ebc to ppc4xx-ebc
ppc4xx: Move EBC model to ppc4xx_devs.c
ppc4xx: Rename ppc405-plb to ppc4xx-plb
ppc4xx: Move PLB model to ppc4xx_devs.c
ppc/ppc405: QOM'ify MAL
ppc/ppc405: QOM'ify PLB
ppc/ppc405: QOM'ify POB
ppc/ppc405: QOM'ify OPBA
ppc/ppc405: QOM'ify EBC
ppc/ppc405: QOM'ify DMA
ppc/ppc405: QOM'ify GPIO
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/e93ded1bf6c9...7dd9d7e0bd29