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[Qemu-commits] [qemu/qemu] 44602a: RISC-V: Allow both Zmmul and M
From: |
Richard Henderson |
Subject: |
[Qemu-commits] [qemu/qemu] 44602a: RISC-V: Allow both Zmmul and M |
Date: |
Thu, 28 Jul 2022 11:27:04 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 44602af8585fd2f331c69e2c071eff39227535ed
https://github.com/qemu/qemu/commit/44602af8585fd2f331c69e2c071eff39227535ed
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date: 2022-07-27 (Wed, 27 Jul 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
RISC-V: Allow both Zmmul and M
We got to talking about how Zmmul and M interact with each other
https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
combination, it just means that the multiplication instructions are
supported even when M is disabled at runtime via misa.
This just stops overriding M from Zmmul, with that the other checks for
the multiplication instructions work as per the ISA.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220714180033.22385-1-palmer@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 54f218363052be210e77d2ada8c0c1e51b3ad6cd
https://github.com/qemu/qemu/commit/54f218363052be210e77d2ada8c0c1e51b3ad6cd
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-07-28 (Thu, 28 Jul 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Fix multi-socket plic configuraiton
Since commit 40244040a7ac, multi-socket configuration with plic is
broken as the hartid for second socket is calculated incorrectly.
The hartid stored in addr_config already includes the offset
for the base hartid for that socket. Adding it again would lead
to segfault while creating the plic device for the virt machine.
qdev_connect_gpio_out was also invoked with incorrect number of gpio
lines.
Fixes: 40244040a7ac (hw/intc: sifive_plic: Avoid overflowing the addr_config
buffer)
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220723090335.671105-1-atishp@rivosinc.com>
[ Changes by AF:
- Change the qdev_connect_gpio_out() numbering
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a17001c42329f809c7f1768925b8089324564312
https://github.com/qemu/qemu/commit/a17001c42329f809c7f1768925b8089324564312
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-28 (Thu, 28 Jul 2022)
Changed paths:
M hw/intc/sifive_plic.c
M target/riscv/cpu.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20220728' of github.com:alistair23/qemu into
staging
Sixth RISC-V PR for QEMU 7.1
This is a PR to go in for RC1. It fixes a segfault that occurs
when using multiple sockets on the RISC-V virt board. It also
includes a small fix to allow both Zmmul and M extensions.
* Allow both Zmmul and M extension
* Fix multi-socket plic configuraiton
# -----BEGIN PGP SIGNATURE-----
#
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# 3amapiJBtYBOwaNZUpb5TZkv/bEDIw==
# =ip1R
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 27 Jul 2022 05:59:28 PM PDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220728' of github.com:alistair23/qemu:
hw/intc: sifive_plic: Fix multi-socket plic configuraiton
RISC-V: Allow both Zmmul and M
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/3e4abe2c9296...a17001c42329