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[Qemu-commits] [qemu/qemu] 9fd012: ppc64: Allocate IRQ lines with qdev_i


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 9fd012: ppc64: Allocate IRQ lines with qdev_init_gpio_in()
Date: Mon, 18 Jul 2022 11:27:50 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 9fd0122e7d365e4b634cc252032ea921f2b4a931
      
https://github.com/qemu/qemu/commit/9fd0122e7d365e4b634cc252032ea921f2b4a931
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xive.c
    M hw/ppc/mac_newworld.c
    M hw/ppc/ppc.c

  Log Message:
  -----------
  ppc64: Allocate IRQ lines with qdev_init_gpio_in()

This replaces the IRQ array 'irq_inputs' with GPIO lines, the goal
being to remove 'irq_inputs' when all CPUs have been converted.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220705145814.461723-2-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 47b60fc6252448c9b8a3cc2296e4b26af57078d3
      
https://github.com/qemu/qemu/commit/47b60fc6252448c9b8a3cc2296e4b26af57078d3
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M hw/ppc/ppc.c
    M hw/ppc/ppc405_uc.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/sam460ex.c
    M hw/ppc/virtex_ml507.c

  Log Message:
  -----------
  ppc/40x: Allocate IRQ lines with qdev_init_gpio_in()

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220705145814.461723-3-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 0f3e0c6fd39af1c10bf170e0463ece341d73e323
      
https://github.com/qemu/qemu/commit/0f3e0c6fd39af1c10bf170e0463ece341d73e323
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/ppc/pegasos2.c
    M hw/ppc/ppc.c
    M hw/ppc/prep.c
    M hw/ppc/prep_systemio.c

  Log Message:
  -----------
  ppc/6xx: Allocate IRQ lines with qdev_init_gpio_in()

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220705145814.461723-4-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 5e66cd0c7802f89e92407ad0a27169d26ffe5b7b
      
https://github.com/qemu/qemu/commit/5e66cd0c7802f89e92407ad0a27169d26ffe5b7b
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M hw/ppc/e500.c
    M hw/ppc/ppc.c

  Log Message:
  -----------
  ppc/e500: Allocate IRQ lines with qdev_init_gpio_in()

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220705145814.461723-5-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 285c471f822a09ceb352e6f73eed42b694173952
      
https://github.com/qemu/qemu/commit/285c471f822a09ceb352e6f73eed42b694173952
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  ppc: Remove unused irq_inputs

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220705145814.461723-6-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: c4b075318eb1e87de5fc942e6b987694a0e677e1
      
https://github.com/qemu/qemu/commit/c4b075318eb1e87de5fc942e6b987694a0e677e1
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M hw/ppc/e500.c
    M hw/ppc/spapr.c

  Log Message:
  -----------
  hw/ppc: pass random seed to fdt

If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc6. The rng-seed node is part of the DT spec. Set
this on the paravirt platforms, spapr and e500, just as is done on other
architectures with paravirt hardware.

Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220712135114.289855-1-Jason@zx2c4.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 1a42c69237a57805b09b50e90878c33100ea2397
      
https://github.com/qemu/qemu/commit/1a42c69237a57805b09b50e90878c33100ea2397
  Author: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc/kvm: Skip current and parent directories in kvmppc_find_cpu_dt

Some systems have /proc/device-tree/cpus/../clock-frequency. However,
this is not the expected path for a CPU device tree directory.

Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220712210810.35514-1-muriloo@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 1315eed69d4810ae297f737b44ee8b63f6589190
      
https://github.com/qemu/qemu/commit/1315eed69d4810ae297f737b44ee8b63f6589190
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Fix gen_priv_exception error value in mfspr/mtspr

The code in linux-user/ppc/cpu_loop.c expects POWERPC_EXCP_PRIV
exception with error POWERPC_EXCP_PRIV_OPC or POWERPC_EXCP_PRIV_REG,
while POWERPC_EXCP_INVAL_SPR is expected in POWERPC_EXCP_INVAL
exceptions. This mismatch caused an EXCP_DUMP with the message "Unknown
privilege violation (03)", as seen in [1].

[1] https://gitlab.com/qemu-project/qemu/-/issues/588

Fixes: 9b2fadda3e01 ("ppc: Rework generation of priv and inval interrupts")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/588
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220627141104.669152-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: efb23674d13f9985510e85f72b1b65a42c367941
      
https://github.com/qemu/qemu/commit/efb23674d13f9985510e85f72b1b65a42c367941
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: fix exception error value in slbfee

Testing on a POWER9 DD2.3, we observed that the Linux kernel delivers a
signal with si_code ILL_PRVOPC (5) when a userspace application tries to
use slbfee. To obtain this behavior on linux-user, we should use
POWERPC_EXCP_PRIV with POWERPC_EXCP_PRIV_OPC.

No functional change is intended for softmmu targets as
gen_hvpriv_exception uses the same 'exception' argument
(POWERPC_EXCP_HV_EMU) for raise_exception_*, and the powerpc_excp_*
methods do not use lower bits of the exception error code when handling
POWERPC_EXCP_{INVAL,PRIV}.

Reported-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220627141104.669152-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: b63fa8b98b2f44669be548d8cd5386e9c990234d
      
https://github.com/qemu/qemu/commit/b63fa8b98b2f44669be548d8cd5386e9c990234d
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: remove mfdcrux and mtdcrux

The only PowerPC implementations with these insns were the 460 and 460F,
which had their definitions removed in [1].

[1] 7ff26aa6c657 ("target/ppc: Remove unused PPC 460 and 460F definitions")

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220627141104.669152-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: e89851798597d93554676cfdcbb2f1e0f38cdb68
      
https://github.com/qemu/qemu/commit/e89851798597d93554676cfdcbb2f1e0f38cdb68
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/timebase_helper.c

  Log Message:
  -----------
  target/ppc: fix exception error code in helper_{load, store}_dcr

POWERPC_EXCP_INVAL should only be or-ed with other constants prefixed
with POWERPC_EXCP_INVAL_. Also, take the opportunity to move both
helpers under #if !defined(CONFIG_USER_ONLY) as the instructions that
use them are privileged.

No functional change is intended, the lower 4 bits of the error code are
ignored by all powerpc_excp_* methods on POWERPC_EXCP_INVAL exceptions.

Reported-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220627141104.669152-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: c35553b5e727dccfabc074e3658b082d63675dcc
      
https://github.com/qemu/qemu/commit/c35553b5e727dccfabc074e3658b082d63675dcc
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/power8-pmu-regs.c.inc

  Log Message:
  -----------
  target/ppc: fix PMU Group A register read/write exceptions

A call to "gen_(hv)priv_exception" should use POWERPC_EXCP_PRIV_* as the
'error' argument instead of POWERPC_EXCP_INVAL_*, and POWERPC_EXCP_FU is
an exception type, not an exception error code. To correctly set
FSCR[IC], we should raise Facility Unavailable with this exception type
and IC value as the error code.

Fixes: 565cb1096733 ("target/ppc: add user read/write functions for MMCR0")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220627141104.669152-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 8e1fedf8cef7a11d0cb7d5b23246e1bd5cf02b2a
      
https://github.com/qemu/qemu/commit/8e1fedf8cef7a11d0cb7d5b23246e1bd5cf02b2a
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: fix exception error code in spr_write_excp_vector

The 'error' argument of gen_inval_exception will be or-ed with
POWERPC_EXCP_INVAL, so it should always be a constant prefixed with
POWERPC_EXCP_INVAL_. No functional change is intended,
spr_write_excp_vector is only used by register_BookE_sprs, and
powerpc_excp_booke ignores the lower 4 bits of the error code on
POWERPC_EXCP_INVAL exceptions.

Also, take the opportunity to replace printf with qemu_log_mask.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220627141104.669152-7-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 016b6e1d9c78cd7981b3d9e8f4f3cedd2ba2055a
      
https://github.com/qemu/qemu/commit/016b6e1d9c78cd7981b3d9e8f4f3cedd2ba2055a
  Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/cpu_init.c
    M target/ppc/insn32.decode
    M target/ppc/translate.c
    A target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move tlbie[l] to decode tree

Also decode RIC, PRS and R operands.

Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220712193741.59134-2-leandro.lupori@eldorado.org.br>
[danielhb: mark bit 31 in @X_tlbie pattern as ignored]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: e7beaea55bd1efcb554b8e021092a2e79a317b61
      
https://github.com/qemu/qemu/commit/e7beaea55bd1efcb554b8e021092a2e79a317b61
  Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/mmu-book3s-v3.h
    M target/ppc/mmu_helper.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implement ISA 3.00 tlbie[l]

This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.

Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220712193741.59134-3-leandro.lupori@eldorado.org.br>
[danielhb: moved 'set' declaration to TLBIE_RIC_PWC block]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 9f0cf041975f76720681b218f217eb23333c7c1a
      
https://github.com/qemu/qemu/commit/9f0cf041975f76720681b218f217eb23333c7c1a
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/translate.c
    M target/ppc/translate/fp-impl.c.inc

  Log Message:
  -----------
  target/ppc: receive DisasContext explicitly in GEN_PRIV

GEN_PRIV and related CHK_* macros just assumed that variable named
"ctx" would be in scope when they are used, and that it would be a
pointer to DisasContext. Change these macros to receive the pointer
explicitly.

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-2-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: fc34e81acd5163ea39eee191ec8846c299ca2662
      
https://github.com/qemu/qemu/commit/fc34e81acd5163ea39eee191ec8846c299ca2662
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/translate.c
    M target/ppc/translate/fixedpoint-impl.c.inc

  Log Message:
  -----------
  target/ppc: add macros to check privilege level

Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-3-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 43507e47e14e92e4460fdd29cf9f3798b401589f
      
https://github.com/qemu/qemu/commit/43507e47e14e92e4460fdd29cf9f3798b401589f
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbie to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-4-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: a1b05c06255c2136bd4076017c48546035a8cb40
      
https://github.com/qemu/qemu/commit/a1b05c06255c2136bd4076017c48546035a8cb40
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbieg to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-5-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 2bfcb7a3160878ca04f2e49d85854c56974194a5
      
https://github.com/qemu/qemu/commit/2bfcb7a3160878ca04f2e49d85854c56974194a5
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbia to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-6-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 0b0ba40fd227be94dec2372df6f6e029e496a0e3
      
https://github.com/qemu/qemu/commit/0b0ba40fd227be94dec2372df6f6e029e496a0e3
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbmte to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-7-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 74a153844ec6ec28162fe2f1301a0efb6ad53205
      
https://github.com/qemu/qemu/commit/74a153844ec6ec28162fe2f1301a0efb6ad53205
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbmfev to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-8-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 41b60e46b8eafb02b79e724c2b7220eff6d3d42e
      
https://github.com/qemu/qemu/commit/41b60e46b8eafb02b79e724c2b7220eff6d3d42e
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbmfee to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-9-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 26d02c9d426761503afb60df3be9f44fb19cf3d0
      
https://github.com/qemu/qemu/commit/26d02c9d426761503afb60df3be9f44fb19cf3d0
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbfee to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-10-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: acc130cf1d4c4191dd3d60a88ac4e055ea0db3ce
      
https://github.com/qemu/qemu/commit/acc130cf1d4c4191dd3d60a88ac4e055ea0db3ce
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/insn32.decode
    M target/ppc/translate.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Move slbsync to decodetree

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-11-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 491a25535c99b838772ff961a39762333f0e852f
      
https://github.com/qemu/qemu/commit/491a25535c99b838772ff961a39762333f0e852f
  Author: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/mmu-hash64.c
    M target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  target/ppc: Implement slbiag

Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220701133507.740619-12-lucas.coutinho@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 3778aa970f21b475ca16befcf271078602104fe6
      
https://github.com/qemu/qemu/commit/3778aa970f21b475ca16befcf271078602104fe6
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/cpu_init.c
    M target/ppc/monitor.c

  Log Message:
  -----------
  target/ppc: check tb_env != 0 before printing TBU/TBL/DECR

When using "-machine none", env->tb_env is not allocated, causing the
segmentation fault reported in issue #85 (launchpad bug #811683). To
avoid this problem, check if the pointer != NULL before calling the
methods to print TBU/TBL/DECR.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/85
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220714172343.80539-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 3c2e80ad2fcf004fcf74bf690dc1c952320a5b52
      
https://github.com/qemu/qemu/commit/3c2e80ad2fcf004fcf74bf690dc1c952320a5b52
  Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_hcall.c
    M target/ppc/mmu-book3s-v3.c
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  ppc: Check partition and process table alignment

Check if partition and process tables are properly aligned, in
their size, according to PowerISA 3.1B, Book III 6.7.6 programming
note. Hardware and KVM also raise an exception in these cases.

Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220628133959.15131-2-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 47e83d9107887c867bad8900ed39e83b79110b66
      
https://github.com/qemu/qemu/commit/47e83d9107887c867bad8900ed39e83b79110b66
  Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  target/ppc: Improve Radix xlate level validation

Check if the number and size of Radix levels are valid on
POWER9/POWER10 CPUs, according to the supported Radix Tree
Configurations described in their User Manuals.

Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220628133959.15131-3-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: d2066bc50d690a6605307eaf0e72a9cf51e6fc25
      
https://github.com/qemu/qemu/commit/d2066bc50d690a6605307eaf0e72a9cf51e6fc25
  Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  target/ppc: Check page dir/table base alignment

According to PowerISA 3.1B, Book III 6.7.6 programming note, the
page directory base addresses are expected to be aligned to their
size. Real hardware seems to rely on that and will access the
wrong address if they are misaligned. This results in a
translation failure even if the page tables seem to be properly
populated.

Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220628133959.15131-4-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: b8bb9bbf4695b89bbdca702a054db0a7a2c8ff2b
      
https://github.com/qemu/qemu/commit/b8bb9bbf4695b89bbdca702a054db0a7a2c8ff2b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xive.c
    M hw/ppc/e500.c
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/ppc/pegasos2.c
    M hw/ppc/ppc.c
    M hw/ppc/ppc405_uc.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/prep.c
    M hw/ppc/prep_systemio.c
    M hw/ppc/sam460ex.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/virtex_ml507.c
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/helper.h
    M target/ppc/insn32.decode
    M target/ppc/kvm.c
    M target/ppc/mmu-book3s-v3.c
    M target/ppc/mmu-book3s-v3.h
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-radix64.c
    M target/ppc/mmu_helper.c
    M target/ppc/monitor.c
    M target/ppc/power8-pmu-regs.c.inc
    M target/ppc/timebase_helper.c
    M target/ppc/translate.c
    M target/ppc/translate/fixedpoint-impl.c.inc
    M target/ppc/translate/fp-impl.c.inc
    A target/ppc/translate/storage-ctrl-impl.c.inc

  Log Message:
  -----------
  Merge tag 'pull-ppc-20220718' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2022-07-18:

This is the last ppc patch queue before the soft freeze. It contains new
TCG instructions and changes, a tricky bug fix in kvmppc_find_cpu_dt()
and other enhancements/fixes.

- tcg and target/ppc:
  - move instructions to decodetree
  - check for bad Radix configs
  - ISA 3.00 tlbie[l]
  - fix gen_*_exception error codes
  - check fortb_env != 0 when printing TBU/TBL/DECR
- fix kvmppc_find_cpu_dt() returning the wrong CPU DT path when there's a
'clock-frequency' property in the root node
- spapr, e500: pass a random seed in /chosen/rng-seed
- all boards: allocate IRQ lines with qdev_init_gpio_in()

# gpg: Signature made Mon 18 Jul 2022 18:19:58 BST
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" 
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20220718' of https://gitlab.com/danielhb/qemu: (30 commits)
  target/ppc: Check page dir/table base alignment
  target/ppc: Improve Radix xlate level validation
  ppc: Check partition and process table alignment
  target/ppc: check tb_env != 0 before printing TBU/TBL/DECR
  target/ppc: Implement slbiag
  target/ppc: Move slbsync to decodetree
  target/ppc: Move slbfee to decodetree
  target/ppc: Move slbmfee to decodetree
  target/ppc: Move slbmfev to decodetree
  target/ppc: Move slbmte to decodetree
  target/ppc: Move slbia to decodetree
  target/ppc: Move slbieg to decodetree
  target/ppc: Move slbie to decodetree
  target/ppc: add macros to check privilege level
  target/ppc: receive DisasContext explicitly in GEN_PRIV
  target/ppc: Implement ISA 3.00 tlbie[l]
  target/ppc: Move tlbie[l] to decode tree
  target/ppc: fix exception error code in spr_write_excp_vector
  target/ppc: fix PMU Group A register read/write exceptions
  target/ppc: fix exception error code in helper_{load, store}_dcr
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/782378973121...b8bb9bbf4695



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