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[Qemu-commits] [qemu/qemu] 524287: hw/arm/virt: dt: add rng-seed propert
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 524287: hw/arm/virt: dt: add rng-seed property |
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Date: |
Thu, 07 Jul 2022 19:32:42 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 5242876f37ca21017e3f6eafbaefaa174babd9b7
https://github.com/qemu/qemu/commit/5242876f37ca21017e3f6eafbaefaa174babd9b7
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M docs/about/deprecated.rst
M docs/system/arm/virt.rst
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: dt: add rng-seed property
In 60592cfed2 ("hw/arm/virt: dt: add kaslr-seed property"), the
kaslr-seed property was added, but the equally as important rng-seed
property was forgotten about, which has identical semantics for a
similar purpose. This commit implements it in exactly the same way as
kaslr-seed. It then changes the name of the disabling option to reflect
that this has more to do with randomness vs determinism, rather than
something particular about kaslr.
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[PMM: added deprecated.rst section for the deprecation]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a4f3791143d8f98a5a9216b94d33a232ebf12c25
https://github.com/qemu/qemu/commit/a4f3791143d8f98a5a9216b94d33a232ebf12c25
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Fix MTE check in sve_ldnfff1_r
The comment was correct, but the test was not:
disable mte if tagged is *not* set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 95047cdeb3d6cb8e4e2fecc82994afbb51b3352e
https://github.com/qemu/qemu/commit/95047cdeb3d6cb8e4e2fecc82994afbb51b3352e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Record tagged bit for user-only in sve_probe_page
Fixes a bug in that we were not honoring MTE from user-only
SVE. Copy the user-only MTE logic from allocation_tag_mem
into sve_probe_page.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 573b8ec70093d3c1b5789f106c5758a7e6c279fb
https://github.com/qemu/qemu/commit/573b8ec70093d3c1b5789f106c5758a7e6c279fb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix code style issues in debug helper functions
Before moving debug system register helper functions to a
different file, fix the code style issues (mostly block
comment syntax) so checkpatch doesn't complain about the
code-motion patch.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220630194116.3438513-2-peter.maydell@linaro.org
Commit: f43ee493c270a27876a55e9636bc4824881d1bbd
https://github.com/qemu/qemu/commit/f43ee493c270a27876a55e9636bc4824881d1bbd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move define_debug_regs() to debug_helper.c
The target/arm/helper.c file is very long and is a grabbag of all
kinds of functionality. We have already a debug_helper.c which has
code for implementing architectural debug. Move the code which
defines the debug-related system registers out to this file also.
This affects the define_debug_regs() function and the various
functions and arrays which are used only by it.
The functions raw_write() and arm_mdcr_el2_eff() and
define_debug_regs() now need to be global rather than local to
helper.c; everything else is pure code movement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220630194116.3438513-3-peter.maydell@linaro.org
Commit: 40b200279c98ea0c223fa5a2bdeb4aee40d4e40e
https://github.com/qemu/qemu/commit/40b200279c98ea0c223fa5a2bdeb4aee40d4e40e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Suppress debug exceptions when OS Lock set
The "OS Lock" in the Arm debug architecture is a way for software
to suppress debug exceptions while it is trying to power down
a CPU and save the state of the breakpoint and watchpoint
registers. In QEMU we implemented the support for writing
the OS Lock bit via OSLAR_EL1 and reading it via OSLSR_EL1,
but didn't implement the actual behaviour.
The required behaviour with the OS Lock set is:
* debug exceptions (apart from BKPT insns) are suppressed
* some MDSCR_EL1 bits allow write access to the corresponding
EDSCR external debug status register that they shadow
(we can ignore this because we don't implement external debug)
* similarly with the OSECCR_EL1 which shadows the EDECCR
(but we don't implement OSECCR_EL1 anyway)
Implement the missing behaviour of suppressing debug
exceptions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220630194116.3438513-4-peter.maydell@linaro.org
Commit: 09754ca867f42d26c5f65350b4c08e958ec9a8da
https://github.com/qemu/qemu/commit/09754ca867f42d26c5f65350b4c08e958ec9a8da
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2
Starting with v7 of the debug architecture, there are three extra
ID registers that add information on top of that provided in
DBGDIDR. These are DBGDEVID, DBGDEVID1 and DBGDEVID2. In the
v7 debug architecture, DBGDEVID is optional, present only of
DBGDIDR.DEVID_imp is set. In v7.1 all three must be present.
Implement the missing registers. Note that we only need to set the
values in the ARMISARegisters struct for the CPUs Cortex-A7, A15,
A53, A57 and A72 (plus the 32-bit 'max' which uses the Cortex-A53
values): earlier CPUs didn't implement v7 of the architecture, and
our other 64-bit CPUs (Cortex-A76, Neoverse-N1 and A64fx) don't have
AArch32 support at EL1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220630194116.3438513-5-peter.maydell@linaro.org
Commit: f94a6df5dd6a7d30436c551b16633767e382d9a0
https://github.com/qemu/qemu/commit/f94a6df5dd6a7d30436c551b16633767e382d9a0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Correctly implement Feat_DoubleLock
The architecture defines the OS DoubleLock as a register which
(similarly to the OS Lock) suppresses debug events for use in CPU
powerdown sequences. This functionality is required in Arm v7 and
v8.0; from v8.2 it becomes optional and in v9 it must not be
implemented.
Currently in QEMU we implement the OSDLR_EL1 register as a NOP. This
is wrong both for the "feature implemented" and the "feature not
implemented" cases: if the feature is implemented then the DLK bit
should read as written and cause suppression of debug exceptions, and
if it is not implemented then the bit must be RAZ/WI.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c2360eaa0262a816faf8032b7762d0c73df2cc62
https://github.com/qemu/qemu/commit/c2360eaa0262a816faf8032b7762d0c73df2cc62
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-07-07 (Thu, 07 Jul 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem
In commit 39a1fd25287f5d we fixed a bug in the handling of LPAE block
descriptors where we weren't correctly zeroing out some RES0 bits.
However this fix has a bug because the calculation of the mask is
done at the wrong width: in
descaddr &= ~(page_size - 1);
page_size is a target_ulong, so in the 'qemu-system-arm' binary it is
only 32 bits, and the effect is that we always zero out the top 32
bits of the calculated address. Fix the calculation by forcing the
mask to be calculated with the same type as descaddr.
This only affects 32-bit CPUs which support LPAE (e.g. cortex-a15)
when used on board models which put RAM or devices above the 4GB
mark and when the 'qemu-system-arm' executable is being used.
It was also masked in 7.0 by the main bug reported in
https://gitlab.com/qemu-project/qemu/-/issues/1078 where the
virt board incorrectly does not enable 'highmem' for 32-bit CPUs.
The workaround is to use 'qemu-system-aarch64' with the same
command line.
Reported-by: He Zhe <zhe.he@windriver.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220627134620.3190252-1-peter.maydell@linaro.org
Fixes: 39a1fd25287f5de ("target/arm: Fix handling of LPAE block descriptors")
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 63b38f6c85acd312c2cab68554abf33adf4ee2b3
https://github.com/qemu/qemu/commit/63b38f6c85acd312c2cab68554abf33adf4ee2b3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-08 (Fri, 08 Jul 2022)
Changed paths:
M docs/about/deprecated.rst
M docs/system/arm/virt.rst
M hw/arm/virt.c
M include/hw/arm/virt.h
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/sve_helper.c
Log Message:
-----------
Merge tag 'pull-target-arm-20220707' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/virt: dt: add rng-seed property
* Fix MTE check in sve_ldnfff1_r
* Record tagged bit for user-only in sve_probe_page
* Correctly implement OS Lock and OS DoubleLock
* Implement DBGDEVID, DBGDEVID1, DBGDEVID2 registers
* Fix qemu-system-arm handling of LPAE block descriptors for highmem
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# gpg: Signature made Thu 07 Jul 2022 05:56:23 PM +0530
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20220707' of
https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem
target/arm: Correctly implement Feat_DoubleLock
target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2
target/arm: Suppress debug exceptions when OS Lock set
target/arm: Move define_debug_regs() to debug_helper.c
target/arm: Fix code style issues in debug helper functions
target/arm: Record tagged bit for user-only in sve_probe_page
target/arm: Fix MTE check in sve_ldnfff1_r
hw/arm/virt: dt: add rng-seed property
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/212267df2b5f...63b38f6c85ac