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Re: [PATCH v12 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC
From: |
Jinjie Ruan |
Subject: |
Re: [PATCH v12 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU |
Date: |
Sun, 7 Apr 2024 10:46:03 +0800 |
User-agent: |
Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 |
On 2024/4/4 22:47, Peter Maydell wrote:
> On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>>
>> Wire the new NMI and VINMI interrupt line from the GIC to each CPU.
>>
>> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> v9:
>> - Rename ARM_CPU_VNMI to ARM_CPU_VINMI.
>> - Update the commit message.
>> v4:
>> - Add Reviewed-by.
>> v3:
>> - Also add VNMI wire.
>> ---
>> hw/arm/virt.c | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> index a9a913aead..ef2e6c2c4d 100644
>> --- a/hw/arm/virt.c
>> +++ b/hw/arm/virt.c
>> @@ -821,7 +821,8 @@ static void create_gic(VirtMachineState *vms,
>> MemoryRegion *mem)
>>
>> /* Wire the outputs from each CPU's generic timer and the GICv3
>> * maintenance interrupt signal to the appropriate GIC PPI inputs,
>> - * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's
>> inputs.
>> + * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
>> + * CPU's inputs.
>> */
>> for (i = 0; i < smp_cpus; i++) {
>> DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
>> @@ -865,6 +866,10 @@ static void create_gic(VirtMachineState *vms,
>> MemoryRegion *mem)
>> qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
>> sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
>> qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
>> + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
>> + qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
>> + sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
>> + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
>> }
>
> This patch needs to go after patch 11. Otherwise at this point
> in the patchseries we are trying to wire up GPIOs on the GIC
> which don't exist, and QEMU will assert:
>
> $ ./build/x86/qemu-system-aarch64 -M virt,gic-version=3
> Unexpected error in object_property_find_err() at ../../qom/object.c:1366:
> qemu-system-aarch64: Property 'arm-gicv3.sysbus-irq[4]' not found
> Aborted (core dumped)
>
> We also need to only connect these up if vms->gic_version
> is not VIRT_GIC_VERSION_2. This is because these GPIOs don't
> exist on the GICv2, and otherwise we again assert if you
> try to wire them up but you're using GICv2:
>
> $ ./build/x86/qemu-system-aarch64 -M virt,gic-version=2
> Unexpected error in object_property_find_err() at ../../qom/object.c:1366:
> qemu-system-aarch64: Property 'arm_gic.sysbus-irq[4]' not found
> Aborted (core dumped)
Thank you! I'll fix them.
>
> thanks
> -- PMM
- [PATCH v12 07/23] target/arm: Add support for NMI in arm_phys_excp_target_el(), (continued)
- [PATCH v12 07/23] target/arm: Add support for NMI in arm_phys_excp_target_el(), Jinjie Ruan, 2024/04/03
- [PATCH v12 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 06/23] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 01/23] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Jinjie Ruan, 2024/04/03
- [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate), Jinjie Ruan, 2024/04/03
- [PATCH v12 05/23] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/04/03
- [PATCH v12 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 14/23] hw/intc/arm_gicv3: Add irq non-maskable property, Jinjie Ruan, 2024/04/03
- [PATCH v12 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 13/23] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Jinjie Ruan, 2024/04/03