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Re: [RFC 4/8] hw/core: Add cache topology options in -smp
From: |
Zhao Liu |
Subject: |
Re: [RFC 4/8] hw/core: Add cache topology options in -smp |
Date: |
Thu, 29 Feb 2024 15:04:42 +0800 |
Hi JeeHeng,
> > diff --git a/hw/core/machine.c b/hw/core/machine.c
> > index 426f71770a84..cb5173927b0d 100644
> > --- a/hw/core/machine.c
> > +++ b/hw/core/machine.c
> > @@ -886,6 +886,10 @@ static void machine_get_smp(Object *obj, Visitor *v,
> > const char *name,
> > .has_cores = true, .cores = ms->smp.cores,
> > .has_threads = true, .threads = ms->smp.threads,
> > .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
> > + .l1d_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1d)),
> > + .l1i_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1i)),
> > + .l2_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l2)),
> > + .l3_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l3)),
>
> Let's standardize the code by adding the 'has_' prefix.
SMPConfiguration is automatically generated in the compilation, and its
prototype is defined in qapi/machine.json like the following code:
> > diff --git a/qapi/machine.json b/qapi/machine.json
> > index d0e7f1f615f3..0a923ac38803 100644
> > --- a/qapi/machine.json
> > +++ b/qapi/machine.json
> > @@ -1650,6 +1650,14 @@
> > #
> > # @threads: number of threads per core
> > #
> > +# @l1d-cache: topology hierarchy of L1 data cache (since 9.0)
> > +#
> > +# @l1i-cache: topology hierarchy of L1 instruction cache (since 9.0)
> > +#
> > +# @l2-cache: topology hierarchy of L2 unified cache (since 9.0)
> > +#
> > +# @l3-cache: topology hierarchy of L3 unified cache (since 9.0)
> > +#
> > # Since: 6.1
> > ##
> > { 'struct': 'SMPConfiguration', 'data': {
> > @@ -1662,7 +1670,11 @@
> > '*modules': 'int',
> > '*cores': 'int',
> > '*threads': 'int',
> > - '*maxcpus': 'int' } }
> > + '*maxcpus': 'int',
> > + '*l1d-cache': 'str',
> > + '*l1i-cache': 'str',
> > + '*l2-cache': 'str',
> > + '*l3-cache': 'str' } }
> >
The gnerated complete structure is (will in build/qapi/qapi-types-machine.h):
struct SMPConfiguration {
bool has_cpus;
int64_t cpus;
bool has_drawers;
int64_t drawers;
bool has_books;
int64_t books;
bool has_sockets;
int64_t sockets;
bool has_dies;
int64_t dies;
bool has_clusters;
int64_t clusters;
bool has_modules;
int64_t modules;
bool has_cores;
int64_t cores;
bool has_threads;
int64_t threads;
bool has_maxcpus;
int64_t maxcpus;
char *l1d_cache;
char *l1i_cache;
char *l2_cache;
char *l3_cache;
};
The int member defined in qapi/machine.json will get their corresponding
status fields as has_* to indicate if user sets those int fields.
For str type, the status field is not needed since NULL is enough to
indicate no user sets that.
Thanks,
Zhao
- [RFC 4/8] hw/core: Add cache topology options in -smp, (continued)
RE: [RFC 4/8] hw/core: Add cache topology options in -smp, JeeHeng Sia, 2024/02/28
- Re: [RFC 4/8] hw/core: Add cache topology options in -smp,
Zhao Liu <=
[RFC 5/8] i386/cpu: Support thread and module level cache topology, Zhao Liu, 2024/02/20
[RFC 6/8] i386/cpu: Update cache topology with machine's configuration, Zhao Liu, 2024/02/20
[RFC 7/8] i386/pc: Support cache topology in -smp for PC machine, Zhao Liu, 2024/02/20
[RFC 8/8] qemu-options: Add the cache topology description of -smp, Zhao Liu, 2024/02/20
Re: [RFC 0/8] Introduce SMP Cache Topology, Philippe Mathieu-Daudé, 2024/02/20