[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH v2 22/22] hw/intc/arm_gicv3: Report the NMI interrupt in gicv
From: |
Jinjie Ruan |
Subject: |
[RFC PATCH v2 22/22] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() |
Date: |
Wed, 21 Feb 2024 13:08:23 +0000 |
In CPU Interface, if the IRQ or FIQ has the superpriority property, report
NMI to the corresponding PE and record the NMI interrupt type.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
hw/intc/arm_gicv3_cpuif.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index f5bf8df32b..87bde1f897 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -931,6 +931,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
/* Tell the CPU about its highest priority pending interrupt */
int irqlevel = 0;
int fiqlevel = 0;
+ int nmilevel = 0;
ARMCPU *cpu = ARM_CPU(cs->cpu);
CPUARMState *env = &cpu->env;
@@ -967,7 +968,10 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
g_assert_not_reached();
}
- if (isfiq) {
+ if (cs->hppi.superprio) {
+ nmilevel = 1;
+ env->nmi_is_irq = !isfiq;
+ } else if (isfiq) {
fiqlevel = 1;
} else {
irqlevel = 1;
@@ -978,6 +982,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
qemu_set_irq(cs->parent_fiq, fiqlevel);
qemu_set_irq(cs->parent_irq, irqlevel);
+ qemu_set_irq(cs->parent_nmi, nmilevel);
}
static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
--
2.34.1
- Re: [RFC PATCH v2 06/22] target/arm: Add support for Non-maskable Interrupt, (continued)
- [RFC PATCH v2 16/22] hw/intc/arm_gicv3: Implement GICD_INMIR, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 09/22] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 05/22] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 13/22] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 22/22] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(),
Jinjie Ruan <=
- [RFC PATCH v2 20/22] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 14/22] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 15/22] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 21/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 12/22] hw/arm/virt: Wire NMI irq line from GIC to CPU, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 01/22] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 02/22] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Jinjie Ruan, 2024/02/21