Re: [PATCH v0 2/2] aspeed: fix hardcode boot address 0

[Cédric Le Goater]

On 2/6/24 02:48, Jamin Lin wrote:
> > -----Original Message-----
> > From: Philippe Mathieu-Daudé <philmd@linaro.org>
> > Sent: Monday, February 5, 2024 9:20 PM
> > To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> > Peter Maydell <peter.maydell@linaro.org>; Andrew Jeffery
> > <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> > list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> > <qemu-devel@nongnu.org>
> > Cc: Troy Lee <troy_lee@aspeedtech.com>
> > Subject: Re: [PATCH v0 2/2] aspeed: fix hardcode boot address 0
> >
> > Hi Jamin,
> >
> > On 5/2/24 10:14, Jamin Lin via wrote:
> > > In the previous design of QEMU model for ASPEED SOCs, it set the boot
> > > address at 0 which was the hardcode setting for ast10x0, ast2600,
> > > ast2500 and ast2400.
> > >
> > > According to the design of ast2700, it has bootmcu which is used for
> > > executing SPL and initialize DRAM,
> >
> > Out of curiosity, what architecture is this MCU?
> MCU is riscv-ibex and its architecture is riscv-32.
>
> > > then, CPUs(cortex-a35)
> > > execute u-boot, kernel and rofs. QEMU will only support
> > > CPU(coretax-a35) parts and the boot address is "0x400000000" for ast2700.
> >
> > OK, but I don't get how you get from here ...
> Our design make MCU execute SPL and copy u-boot image from SPI to DRAM at 
> address 0x400000000 at SPL boot stage.
> However, QEMU will only support to emulate CPU sides (coretex-a35) for ast2700, 

The fby35 is an example of a machine with two ARM SoCs : ast1030-a1
and ast2600-a3. There is work in progress for heterogeneous QEMU
machines and It might be possible to model RISC-V and ARM one day.

> that was why we want to change the boot address at 0x400000000
> And use the following start command by QEMU.
>
> ./qemu-system-aarch64 -M ast2750-evb -nographic -m 8G \
>   -device loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on \
>   -device loader,addr=$((0x400000000 + 
> ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb,force-raw=on \
>   ---
>   ---
ok. Makes sense.
 
> By the way, I will send a new patch series to support ast2700 in two weeks and
> We set memory map for ast2700 as following.
>
> static const hwaddr aspeed_soc_ast2700_memmap[] = {
>      [ASPEED_DEV_SPI_BOOT]  =  0x400000000,
>      [ASPEED_DEV_SRAM]      =  0x10000000,

Excellent !

Thanks,

C.