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Re: [PULL 00/36] HW core patches for 2024-01-19
From: |
Peter Maydell |
Subject: |
Re: [PULL 00/36] HW core patches for 2024-01-19 |
Date: |
Fri, 19 Jan 2024 16:41:25 +0000 |
On Fri, 19 Jan 2024 at 11:37, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> The following changes since commit 88cf5fec91e50cd34bc002b633b4116228db0bc8:
>
> Merge tag 'pull-target-arm-20240118' of
> https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-01-18
> 12:48:17 +0000)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/hw-cpus-20240119
>
> for you to fetch changes up to 7ec5d7d91215815e885d2b38e62256e8fd8e2bce:
>
> configure: Add linux header compile support for LoongArch (2024-01-19
> 12:28:59 +0100)
>
> ----------------------------------------------------------------
> HW core patch queue
>
> . Deprecate unmaintained SH-4 models (Samuel)
> . HPET: Convert DPRINTF calls to trace events (Daniel)
> . Implement buffered block writes in Intel PFlash (Gerd)
> . Ignore ELF loadable segments with zero size (Bin)
> . ESP/NCR53C9x: PCI DMA fixes (Mark)
> . PIIX: Simplify Xen PCI IRQ routing (Bernhard)
> . Restrict CPU 'start-powered-off' property to sysemu (Phil)
>
> . target/alpha: Only build sys_helper.c on system emulation (Phil)
> . target/xtensa: Use generic instruction breakpoint API & add test (Max)
> . Restrict icount to system emulation (Phil)
> . Do not set CPUState TCG-specific flags in non-TCG accels (Phil)
> . Cleanup TCG tb_invalidate API (Phil)
> . Correct LoongArch/KVM include path (Bibo)
> . Do not ignore throttle errors in crypto backends (Phil)
>
> . MAINTAINERS updates (Raphael, Zhao)
>
> Note the following checkpatch error is deliberately ignored:
>
> ERROR: space prohibited after that '&&' (ctx:ExW)
> #143: FILE: accel/tcg/watchpoint.c:119:
> + && cc->tcg_ops->debug_check_watchpoint
> ^
> ----------------------------------------------------------------
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
- [PULL 28/36] target/riscv: Rename tcg_cpu_FOO() to include 'riscv', (continued)
- [PULL 28/36] target/riscv: Rename tcg_cpu_FOO() to include 'riscv', Philippe Mathieu-Daudé, 2024/01/19
- [PULL 29/36] hw/scsi/esp-pci: use correct address register for PCI DMA transfers, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 30/36] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 31/36] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 32/36] hw/scsi/esp-pci: set DMA_STAT_BCMBLT when BLAST command issued, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 33/36] hw/elf_ops: Ignore loadable segments with zero size, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 34/36] MAINTAINERS: Update Raphael Norwitz email, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 35/36] MAINTAINERS: Update hw/core/cpu.c entry, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 36/36] configure: Add linux header compile support for LoongArch, Philippe Mathieu-Daudé, 2024/01/19
- Re: [PULL 00/36] HW core patches for 2024-01-19,
Peter Maydell <=