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[PULL 13/36] target/arm: Ensure icount is enabled when emulating INST_RE
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 13/36] target/arm: Ensure icount is enabled when emulating INST_RETIRED |
Date: |
Fri, 19 Jan 2024 12:34:42 +0100 |
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is enabled as ICOUNT_PRECISE.
PMU events are TCG-only, hardware accelerators handle them
directly. Unfortunately we register the events in non-TCG builds,
leading to linking error such:
ld: Undefined symbols:
_icount_to_ns, referenced from:
_instructions_ns_per in target_arm_helper.c.o
clang: error: linker command failed with exit code 1 (use -v to see
invocation)
As a kludge, give a hint to the compiler by asserting the
pm_event::get_count() and pm_event::ns_per_count() handler will
only be called under this icount mode.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231208113529.74067-5-philmd@linaro.org>
---
target/arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 49665bb763..e068d35383 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -954,11 +954,13 @@ static bool instructions_supported(CPUARMState *env)
static uint64_t instructions_get_count(CPUARMState *env)
{
+ assert(icount_enabled() == ICOUNT_PRECISE);
return (uint64_t)icount_get_raw();
}
static int64_t instructions_ns_per(uint64_t icount)
{
+ assert(icount_enabled() == ICOUNT_PRECISE);
return icount_to_ns((int64_t)icount);
}
#endif
--
2.41.0
- [PULL 03/36] accel: Do not set CPUState::tcg_cflags in non-TCG accels, (continued)
- [PULL 03/36] accel: Do not set CPUState::tcg_cflags in non-TCG accels, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 04/36] accel: Do not set CPUState::can_do_io in non-TCG accels, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 05/36] target/xtensa: use generic instruction breakpoint infrastructure, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 06/36] tests/tcg/xtensa: add icount/ibreak priority test, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 07/36] accel/tcg: Remove unused tb_invalidate_phys_addr(), Philippe Mathieu-Daudé, 2024/01/19
- [PULL 08/36] accel/tcg: Remove tb_invalidate_phys_page() from system emulation, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 09/36] target/alpha: Extract clk_helper.c from sys_helper.c, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 10/36] target/alpha: Only build sys_helper.c on system emulation, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 11/36] system/cpu-timers: Have icount_configure() return a boolean, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 12/36] system/cpu-timers: Introduce ICountMode enumerator, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 13/36] target/arm: Ensure icount is enabled when emulating INST_RETIRED,
Philippe Mathieu-Daudé <=
- [PULL 14/36] util/async: Only call icount_notify_exit() if icount is enabled, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 15/36] target/sh4: Deprecate the shix machine, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 16/36] hw/block: Deprecate the TC58128 block device, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 17/36] hw/i386/pc_piix: Make piix_intx_routing_notifier_xen() more device independent, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 18/36] hw/pflash: refactor pflash_data_write(), Philippe Mathieu-Daudé, 2024/01/19
- [PULL 19/36] hw/pflash: use ldn_{be,le}_p and stn_{be,le}_p, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 20/36] hw/pflash: implement update buffer for block writes, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 21/36] system/replay: Restrict icount to system emulation, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 22/36] system/watchpoint: Move TCG specific code to accel/tcg/, Philippe Mathieu-Daudé, 2024/01/19
- [PULL 23/36] cpus: Restrict 'start-powered-off' property to system emulation, Philippe Mathieu-Daudé, 2024/01/19