Re: [PATCH v9 08/10] hw/net: GMAC Rx Implementation

[Peter Maydell]

On Tue, 19 Dec 2023 at 21:33, Nabih Estefan <nabihestefan@google.com> wrote:
>
> From: Nabih Estefan Diaz <nabihestefan@google.com>
>
> - Implementation of Receive function for packets
> - Implementation for reading and writing from and to descriptors in
>   memory for Rx
>
> When RX starts, we need to flush the queued packets so that they
> can be received by the GMAC device. Without this it won't work
> with TAP NIC device.
>
> When RX descriptor list is full, it returns a DMA_STATUS for software to 
> handle it. But there's no way to indicate the software ha handled all RX 
> descriptors and the whole pipeline stalls.

Please make sure you line wrap commit messages at an
appropriate line length.

> We do something similar to NPCM7XX EMC to handle this case.
>
> 1. Return packet size when RX descriptor is full, effectively dropping these 
> packets in such a case.
> 2. When software clears RX descriptor full bit, continue receiving further 
> packets by flushing QEMU packet queue.
>
> Signed-off-by: Hao Wu <wuhaotsh@google.com>
> Signed-off-by: Nabih Estefan <nabihestefan@google.com>
> Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
> ---

> +    /* write frame part to memory */
> +    if (dma_memory_write(&address_space_memory, (uint64_t) rx_buf_addr,
> +                         *frame_ptr, to_transfer, MEMTXATTRS_UNSPECIFIED))
> +    {

Our coding style says the open brace of an if goes on the same line,
not on a line of its own.

> +        return -1;
> +    }

thanks
-- PMM