[PATCH 20/33] hw/cpu/arm: Consolidate check on max GIC spi supported

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/cpu/cortex_mpcore.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c
index c9ba254818..75324268fa 100644
--- a/hw/cpu/cortex_mpcore.c
+++ b/hw/cpu/cortex_mpcore.c
@@ -43,6 +43,13 @@ static void cortex_mpcore_priv_realize(DeviceState *dev, 
Error **errp)
     CortexMPPrivClass *k = CORTEX_MPCORE_PRIV_GET_CLASS(dev);
     DeviceState *gicdev = DEVICE(&s->gic);
 
+    if (s->gic_spi_num > k->gic_spi_max) {
+        error_setg(errp,
+                   "At most %u GIC SPI are supported (requested %u)",
+                   k->gic_spi_max, s->gic_spi_num);
+        return;
+    }
+
     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cores);
     qdev_prop_set_uint32(gicdev, "num-irq", s->gic_spi_num);
     if (k->gic_priority_bits) {
-- 
2.41.0