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Re: [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10


From: Cédric Le Goater
Subject: Re: [PATCH 09/11] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
Date: Wed, 25 Oct 2023 09:12:34 +0200
User-agent: Mozilla Thunderbird

On 10/24/23 18:24, Philippe Mathieu-Daudé wrote:
The v7-M core is specific to the Aspeed 10x0 series,
remove it from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>


Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.


---
  include/hw/arm/aspeed_soc.h |  5 ++---
  hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
  hw/arm/fby35.c              | 13 ++++++++-----
  3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index ee7926b81c..2118a441f7 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -47,13 +47,10 @@
  #define ASPEED_JTAG_NUM  2
struct AspeedSoCState {
-    /*< private >*/
      DeviceState parent;
- /*< public >*/
      ARMCPU cpu[ASPEED_CPUS_NUM];
      A15MPPrivState     a7mpcore;
-    ARMv7MState        armv7m;
      MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
@@ -117,6 +114,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, 
ASPEED2600_SOC)
struct Aspeed10x0SoCState {
      AspeedSoCState parent;
+
+    ARMv7MState armv7m;
  };
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 1c15bf422f..8becb146a8 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -101,13 +101,15 @@ static const int aspeed_soc_ast1030_irqmap[] = {
static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
  {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
  }
static void aspeed_soc_ast1030_init(Object *obj)
  {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      char socname[8];
@@ -118,7 +120,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
          g_assert_not_reached();
      }
- object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); @@ -185,6 +187,7 @@ static void aspeed_soc_ast1030_init(Object *obj) static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
  {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
      AspeedSoCState *s = ASPEED_SOC(dev_soc);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      DeviceState *armv7m;
@@ -206,17 +209,17 @@ static void aspeed_soc_ast1030_realize(DeviceState 
*dev_soc, Error **errp)
                                    0x40000);
/* AST1030 CPU Core */
-    armv7m = DEVICE(&s->armv7m);
+    armv7m = DEVICE(&a->armv7m);
      qdev_prop_set_uint32(armv7m, "num-irq", 256);
      qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
      qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
-    object_property_set_link(OBJECT(&s->armv7m), "memory",
+    object_property_set_link(OBJECT(&a->armv7m), "memory",
                               OBJECT(s->memory), &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* Internal SRAM */
      sram_name = g_strdup_printf("aspeed.sram.%d",
-                                CPU(s->armv7m.cpu)->cpu_index);
+                                CPU(a->armv7m.cpu)->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 
&err);
      if (err != NULL) {
          error_propagate(errp, err);
@@ -249,7 +252,7 @@ static void aspeed_soc_ast1030_realize(DeviceState 
*dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, 
sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST1030 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -261,7 +264,7 @@ static void aspeed_soc_ast1030_realize(DeviceState 
*dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, 
sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST1030 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -290,19 +293,19 @@ static void aspeed_soc_ast1030_realize(DeviceState 
*dev_soc, Error **errp)
       * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + 
aspeed_lpc_kcs_1));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + 
aspeed_lpc_kcs_2));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + 
aspeed_lpc_kcs_3));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + 
aspeed_lpc_kcs_4));
/* UART */
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index f2ff6c1abf..c8bc75d870 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -28,7 +28,7 @@ struct Fby35State {
      Clock *bic_sysclk;
AspeedSoCState bmc;
-    AspeedSoCState bic;
+    Aspeed10x0SoCState bic;
bool mmio_exec;
  };
@@ -114,10 +114,13 @@ static void fby35_bmc_init(Fby35State *s)
static void fby35_bic_init(Fby35State *s)
  {
+    AspeedSoCState *soc;
+
      s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
      clock_set_hz(s->bic_sysclk, 200000000ULL);
object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
+    soc = ASPEED_SOC(&s->bic);
memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
                         UINT64_MAX);
@@ -125,12 +128,12 @@ static void fby35_bic_init(Fby35State *s)
      qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
      object_property_set_link(OBJECT(&s->bic), "memory", 
OBJECT(&s->bic_memory),
                               &error_abort);
-    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
      qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
- aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
-    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
-    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
+    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
+    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
+    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
  }
static void fby35_init(MachineState *machine)




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