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RE: [PATCH RFC V2 16/37] hw/acpi: Update CPUs AML with cpu-(ctrl)dev cha


From: Salil Mehta
Subject: RE: [PATCH RFC V2 16/37] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
Date: Mon, 16 Oct 2023 21:57:24 +0000

> From: Gavin Shan <gshan@redhat.com>
> Sent: Thursday, September 28, 2023 2:26 AM
> To: Salil Mehta <salil.mehta@huawei.com>; qemu-devel@nongnu.org; qemu-
> arm@nongnu.org
> Cc: maz@kernel.org; jean-philippe@linaro.org; Jonathan Cameron
> <jonathan.cameron@huawei.com>; lpieralisi@kernel.org;
> peter.maydell@linaro.org; richard.henderson@linaro.org;
> imammedo@redhat.com; andrew.jones@linux.dev; david@redhat.com;
> philmd@linaro.org; eric.auger@redhat.com; will@kernel.org; ardb@kernel.org;
> oliver.upton@linux.dev; pbonzini@redhat.com; mst@redhat.com;
> rafael@kernel.org; borntraeger@linux.ibm.com; alex.bennee@linaro.org;
> linux@armlinux.org.uk; darren@os.amperecomputing.com;
> ilkka@os.amperecomputing.com; vishnu@os.amperecomputing.com;
> karl.heubaum@oracle.com; miguel.luis@oracle.com; salil.mehta@opnsrc.net;
> zhukeqian <zhukeqian1@huawei.com>; wangxiongfeng (C)
> <wangxiongfeng2@huawei.com>; wangyanan (Y) <wangyanan55@huawei.com>;
> jiakernel2@gmail.com; maobibo@loongson.cn; lixianglai@loongson.cn
> Subject: Re: [PATCH RFC V2 16/37] hw/acpi: Update CPUs AML with cpu-
> (ctrl)dev change
> 
> On 9/26/23 20:04, Salil Mehta wrote:
> > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is
> based on
> > PCI and is IO port based and hence existing cpus AML code assumes _CRS 
> > objects
> 
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>                            . The existing AML code assumes _CRS object
> > would evaluate to a system resource which describes IO Port address. But
> on ARM
>    ^^^^^^^^^^^^^^^^^^^
>    is evaluated to a
> 
> > arch CPUs control device(\\_SB.PRES) register interface is memory-mapped
> hence
> > _CRS object should evaluate to system resource which describes memory-mapped
>                ^^^^^^
>                should be evaluated
> > base address.
> >
> > This cpus AML code change updates the existing inerface of the build cpus 
> > AML
> > function to accept both IO/MEMORY type regions and update the _CRS object
> > correspondingly.
> >
> > NOTE: Beside above CPU scan shall be triggered when OSPM evaluates _EVT 
> > method
> >        part of the GED framework which is covered in subsequent patch.
> >
> > Co-developed-by: Salil Mehta <salil.mehta@huawei.com>
> > Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> > Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
> > Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
> > Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> > ---
> >   hw/acpi/cpu.c         | 23 ++++++++++++++++-------
> >   hw/i386/acpi-build.c  |  2 +-
> >   include/hw/acpi/cpu.h |  5 +++--
> >   3 files changed, 20 insertions(+), 10 deletions(-)
> >
> 
> I guess the commit log can be simplified to:
> 
> The CPU hotplug register block is declared as a IO region on x86, or a memory
> region on arm64 in build_cpus_aml(), as part of the generic container device
> (\\_SB.PCI0 or \\_SB.PRES).
> 
> Adapt build_cpus_aml() so that IO region and memory region can be handled
> in the mean while.
> 
> Reviewed-by: Gavin Shan <gshan@redhat.com>

Has been reviewed already part of architecture agnostic patch-set,


4764CF47-47CA-4685-805C-BBE6310BE164@oracle.com/T/#md615c6d3464e7178214785501e7035bf977886f2">https://lore.kernel.org/qemu-devel/4764CF47-47CA-4685-805C-BBE6310BE164@oracle.com/T/#md615c6d3464e7178214785501e7035bf977886f2


Thanks
Salil.



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