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Re: [PATCH v4 05/24] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu
From: |
Peter Maydell |
Subject: |
Re: [PATCH v4 05/24] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx |
Date: |
Fri, 14 Oct 2022 19:09:39 +0100 |
On Tue, 11 Oct 2022 at 04:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb.
> Flush the tlb when invalidating stage 1+2 translations. Re-use
> alle1_tlbmask() for other instances of EL1&0 + Stage2.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v4: Implement the IPAS2 and RIPAS2 tlb flushing insns;
> Reuse alle1_tlbmask to fix aa32 and vttbr flushing.
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v4 00/24] target/arm: Implement FEAT_HAFDBS, Richard Henderson, 2022/10/10
- [PATCH v4 02/24] target/arm: Use probe_access_full for MTE, Richard Henderson, 2022/10/10
- [PATCH v4 01/24] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/10/10
- [PATCH v4 08/24] target/arm: Plumb debug into S1Translate, Richard Henderson, 2022/10/10
- [PATCH v4 03/24] target/arm: Use probe_access_full for BTI, Richard Henderson, 2022/10/10
- [PATCH v4 05/24] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx, Richard Henderson, 2022/10/10
- Re: [PATCH v4 05/24] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx,
Peter Maydell <=
- [PATCH v4 06/24] target/arm: Restrict tlb flush from vttbr_write to vmid change, Richard Henderson, 2022/10/10
- [PATCH v4 04/24] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Richard Henderson, 2022/10/10
- [PATCH v4 07/24] target/arm: Split out S1Translate type, Richard Henderson, 2022/10/10
- [PATCH v4 11/24] target/arm: Split out get_phys_addr_twostage, Richard Henderson, 2022/10/10
- [PATCH v4 13/24] target/arm: Add ptw_idx to S1Translate, Richard Henderson, 2022/10/10
- [PATCH v4 12/24] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/10/10