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[PATCH v4 24/24] target/arm: Use the max page size in a 2-stage ptw
From: |
Richard Henderson |
Subject: |
[PATCH v4 24/24] target/arm: Use the max page size in a 2-stage ptw |
Date: |
Mon, 10 Oct 2022 20:19:11 -0700 |
We had only been reporting the stage2 page size. This causes
problems if stage1 is using a larger page size (16k, 2M, etc),
but stage2 is using a smaller page size, because cputlb does
not set large_page_{addr,mask} properly.
Fix by using the max of the two page sizes.
Reported-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 0dbbb7d4d4..b8934765ec 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2584,7 +2584,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
ARMMMUFaultInfo *fi)
{
hwaddr ipa;
- int s1_prot;
+ int s1_prot, s1_lgpgsz;
bool is_secure = ptw->in_secure;
bool ret, ipa_secure, s2walk_secure;
ARMCacheAttrs cacheattrs1;
@@ -2620,6 +2620,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
* Save the stage1 results so that we may merge prot and cacheattrs later.
*/
s1_prot = result->f.prot;
+ s1_lgpgsz = result->f.lg_page_size;
cacheattrs1 = result->cacheattrs;
memset(result, 0, sizeof(*result));
@@ -2634,6 +2635,14 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
return ret;
}
+ /*
+ * Use the maximum of the S1 & S2 page size, so that invalidation
+ * of pages > TARGET_PAGE_SIZE works correctly.
+ */
+ if (result->f.lg_page_size < s1_lgpgsz) {
+ result->f.lg_page_size = s1_lgpgsz;
+ }
+
/* Combine the S1 and S2 cache attributes. */
hcr = arm_hcr_el2_eff_secstate(env, is_secure);
if (hcr & HCR_DC) {
--
2.34.1
- [PATCH v4 16/24] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, (continued)
- [PATCH v4 16/24] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Richard Henderson, 2022/10/10
- [PATCH v4 17/24] target/arm: Add ARMFault_UnsuppAtomicUpdate, Richard Henderson, 2022/10/10
- [PATCH v4 18/24] target/arm: Remove loop from get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 10/24] target/arm: Use softmmu tlbs for page table walking, Richard Henderson, 2022/10/10
- [PATCH v4 21/24] target/arm: Consider GP an attribute in get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 20/24] target/arm: Don't shift attrs in get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 23/24] target/arm: Implement FEAT_HAFDBS, dirty bit portion, Richard Henderson, 2022/10/10
- [PATCH v4 22/24] target/arm: Implement FEAT_HAFDBS, access flag portion, Richard Henderson, 2022/10/10
- [PATCH v4 24/24] target/arm: Use the max page size in a 2-stage ptw,
Richard Henderson <=
- Re: [PATCH v4 00/24] target/arm: Implement FEAT_HAFDBS, Peter Maydell, 2022/10/17