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[PATCH v4 21/24] target/arm: Consider GP an attribute in get_phys_addr_l
From: |
Richard Henderson |
Subject: |
[PATCH v4 21/24] target/arm: Consider GP an attribute in get_phys_addr_lpae |
Date: |
Mon, 10 Oct 2022 20:19:08 -0700 |
Both GP and DBM are in the upper attribute block.
Extend the computation of attrs to include them,
then simplify the setting of guarded.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 2227d2a2fd..8db635ca98 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1079,7 +1079,6 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
uint32_t el = regime_el(env, mmu_idx);
uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el);
- bool guarded = false;
uint64_t descriptor;
bool nstable;
@@ -1338,7 +1337,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
descaddr &= ~(hwaddr)(page_size - 1);
descaddr |= (address & (page_size - 1));
/* Extract attributes from the descriptor */
- attrs = descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 12));
+ attrs = descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
/* Stage 2 table descriptors do not include any attribute fields */
@@ -1346,7 +1345,6 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
}
/* Merge in attributes from table descriptors */
attrs |= nstable << 5; /* NS */
- guarded = extract64(descriptor, 50, 1); /* GP */
if (param.hpd) {
/* HPD disables all the table attributes except NSTable. */
goto skip_attrs;
@@ -1399,7 +1397,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
/* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
- result->f.guarded = guarded;
+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
}
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
--
2.34.1
- Re: [PATCH v4 13/24] target/arm: Add ptw_idx to S1Translate, (continued)
- [PATCH v4 12/24] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/10/10
- [PATCH v4 14/24] target/arm: Add isar predicates for FEAT_HAFDBS, Richard Henderson, 2022/10/10
- [PATCH v4 15/24] target/arm: Extract HA and HD in aa64_va_parameters, Richard Henderson, 2022/10/10
- [PATCH v4 09/24] target/arm: Move be test for regime into S1TranslateResult, Richard Henderson, 2022/10/10
- [PATCH v4 19/24] target/arm: Fix fault reporting in get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 16/24] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Richard Henderson, 2022/10/10
- [PATCH v4 17/24] target/arm: Add ARMFault_UnsuppAtomicUpdate, Richard Henderson, 2022/10/10
- [PATCH v4 18/24] target/arm: Remove loop from get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 10/24] target/arm: Use softmmu tlbs for page table walking, Richard Henderson, 2022/10/10
- [PATCH v4 21/24] target/arm: Consider GP an attribute in get_phys_addr_lpae,
Richard Henderson <=
- [PATCH v4 20/24] target/arm: Don't shift attrs in get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 23/24] target/arm: Implement FEAT_HAFDBS, dirty bit portion, Richard Henderson, 2022/10/10
- [PATCH v4 22/24] target/arm: Implement FEAT_HAFDBS, access flag portion, Richard Henderson, 2022/10/10
- [PATCH v4 24/24] target/arm: Use the max page size in a 2-stage ptw, Richard Henderson, 2022/10/10
- Re: [PATCH v4 00/24] target/arm: Implement FEAT_HAFDBS, Peter Maydell, 2022/10/17