Re: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking

[Richard Henderson]

On 10/7/22 02:01, Peter Maydell wrote:
> The upcoming v8R support has its stage 2 attributes in the MAIR
> format, so it might be a little awkward to assume the v8A-stage-2
> format here rather than being able to add the "if !is_s2_format"
> condition. I guess we'll deal with that when we get to it...

Ah.  I had wondered whether it would be better to convert the result here, so that we 
always have the MAIR format.  I decided against it within the scope of this patch set 
because it meant that I kept the existing s1+s2 attribute merging logic unchanged.

> > +    /*
> > +     * Allow S1_ptw_translate to see any fault generated here.
> > +     * Since this may recurse, read and clear.
> > +     */
> > +    fi = cpu->env.tlb_fi;
> > +    if (fi) {
> > +        cpu->env.tlb_fi = NULL;
> > +    } else {
> > +        fi = memset(&local_fi, 0, sizeof(local_fi));
> > +    }
>
> This makes two architectures now that want to do "call a probe_access
> function, and get information that's known in the architecture-specific
> tlb_fill function", and need to do it via this awkward "have tlb_fill
> know that it should stash the info away in the CPU state struct somewhere"
> trick (the other being s390 tlb_fill_exc/tlb_fill_tec). But I don't
> really have a better idea...

A better idea would be most welcome, if anyone has one...  :-)


r~