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[PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write
From: |
Richard Henderson |
Subject: |
[PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write |
Date: |
Sat, 1 Oct 2022 09:22:45 -0700 |
Use get_phys_addr_with_secure directly. For a-profile, this is the
one place where the value of is_secure may not equal arm_is_secure(env).
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 772218f0d2..3adeb4cab4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3188,7 +3188,8 @@ static CPAccessResult ats_access(CPUARMState *env, const
ARMCPRegInfo *ri,
#ifdef CONFIG_TCG
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
- MMUAccessType access_type, ARMMMUIdx mmu_idx)
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
+ bool is_secure)
{
bool ret;
uint64_t par64;
@@ -3196,7 +3197,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
ARMMMUFaultInfo fi = {};
GetPhysAddrResult res = {};
- ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
+ ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx,
+ is_secure, &res, &fi);
/*
* ATS operations only do S1 or S1+S2 translations, so we never
@@ -3368,6 +3370,7 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_SE3;
+ secure = true;
break;
case 2:
g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
@@ -3389,6 +3392,7 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_SE10_0;
+ secure = true;
break;
case 2:
g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
@@ -3404,16 +3408,18 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
mmu_idx = ARMMMUIdx_E10_1;
+ secure = false;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
mmu_idx = ARMMMUIdx_E10_0;
+ secure = false;
break;
default:
g_assert_not_reached();
}
- par64 = do_ats_write(env, value, access_type, mmu_idx);
+ par64 = do_ats_write(env, value, access_type, mmu_idx, secure);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
#else
@@ -3429,7 +3435,8 @@ static void ats1h_write(CPUARMState *env, const
ARMCPRegInfo *ri,
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
- par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
+ /* There is no SecureEL2 for AArch32. */
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
#else
@@ -3472,6 +3479,7 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx = ARMMMUIdx_SE3;
+ secure = true;
break;
default:
g_assert_not_reached();
@@ -3490,7 +3498,8 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
g_assert_not_reached();
}
- env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
+ env->cp15.par_el[1] = do_ats_write(env, value, access_type,
+ mmu_idx, secure);
#else
/* Handled by hardware accelerator. */
g_assert_not_reached();
--
2.34.1
- [PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate, (continued)
- [PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/10/01
- [PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/10/01
- [PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/10/01
- [PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/10/01
- [PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled, Richard Henderson, 2022/10/01
- [PATCH v3 20/42] target/arm: Use tlb_set_page_full, Richard Henderson, 2022/10/01
- [PATCH v3 22/42] target/arm: Use probe_access_full for MTE, Richard Henderson, 2022/10/01
- [PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write,
Richard Henderson <=
- [PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/10/01
- [PATCH v3 18/42] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/10/01
- [PATCH v3 23/42] target/arm: Use probe_access_full for BTI, Richard Henderson, 2022/10/01
- [PATCH v3 24/42] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Richard Henderson, 2022/10/01
- [PATCH v3 21/42] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/10/01
- [PATCH v3 25/42] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx, Richard Henderson, 2022/10/01