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Re: [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc.
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc. |
Date: |
Thu, 20 Jan 2022 16:01:06 +0000 |
On Tue, 11 Jan 2022 at 08:46, Troy Lee <troy_lee@aspeedtech.com> wrote:
>
> v3:
> - Remove unrelated changes to SPI2 address
> - Remove controller irq line
>
> v2: Rebase to mainline QEMU
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
This turns out not to build on macOS or on 32-bit hosts
because of format string issues -- you can't portably
use %lx to print uint64_t or hwaddr types. I have folded
in the following fix:
diff --git a/hw/misc/aspeed_i3c.c b/hw/misc/aspeed_i3c.c
index 43771d768ad..f54f5da522b 100644
--- a/hw/misc/aspeed_i3c.c
+++ b/hw/misc/aspeed_i3c.c
@@ -150,7 +150,8 @@ static void aspeed_i3c_device_write(void *opaque,
hwaddr offset,
case R_I3C_VER_TYPE:
case R_EXTENDED_CAPABILITY:
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: write to readonly register[%02lx] = %08lx\n",
+ "%s: write to readonly register[0x%02" HWADDR_PRIx
+ "] = 0x%08" PRIx64 "\n",
__func__, offset, value);
break;
case R_RX_TX_DATA_PORT:
@@ -231,13 +232,15 @@ static void aspeed_i3c_write(void *opaque,
case R_I3C6_REG1:
if (data & R_I3C1_REG1_I2C_MODE_MASK) {
qemu_log_mask(LOG_UNIMP,
- "%s: Not support I2C mode [%08lx]=%08lx",
+ "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx
+ "]=%08" PRIx64 "\n",
__func__, addr << 2, data);
break;
}
if (data & R_I3C1_REG1_SA_EN_MASK) {
qemu_log_mask(LOG_UNIMP,
- "%s: Not support slave mode [%08lx]=%08lx",
+ "%s: Unsupported slave mode [%08" HWADDR_PRIx
+ "]=0x%08" PRIx64 "\n",
__func__, addr << 2, data);
break;
}
which also includes a small grammar fix, adds the missing
trailing newlines, and includes the "0x" prefix to make it
clearer to the user that the values printed are hex.
thanks
-- PMM