Re: [RFC PATCH 3/6] hw/arm: wire-up memory from the Pico board and the SoC

[Philippe Mathieu-Daudé]

On 1/10/22 18:51, Alex Bennée wrote:
> All the memory aside from the external flash is a feature of the SoC
> itself. However the flash is part of the board and different RP2040
> boards can choose to wire up different amounts of it.
> 
> For now add unimplemented devices for all the rp2040 peripheral
> blocks. Before we can boot more of the ROM we will need to model at
> least the SIO and CLOCKS blocks.
> 
> For now CPU#1 starts disabled as it needs a working CPUID register so
> it can identify itself before sleeping.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>  include/hw/arm/rp2040.h |   9 +++-
>  hw/arm/raspi_pico.c     |  20 +++++++
>  hw/arm/rp2040.c         | 113 ++++++++++++++++++++++++++++++++++++++--
>  3 files changed, 137 insertions(+), 5 deletions(-)

> +static Property rp2040_soc_properties[] = {
> +    DEFINE_PROP_LINK("memory", RP2040State, memory, TYPE_MEMORY_REGION,
> +                     MemoryRegion *),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
>  static void rp2040_class_init(ObjectClass *oc, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -61,14 +167,13 @@ static void rp2040_class_init(ObjectClass *oc, void 
> *data)
>  
>      bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m0");
>      dc->realize = rp2040_realize;
> -    /* any props? */
> +    device_class_set_props(dc, rp2040_soc_properties);
>  };
>  
>  static const TypeInfo rp2040_types[] = {
>      {
>          .name           = TYPE_RP2040,
> -        /* .parent         = TYPE_SYS_BUS_DEVICE, */
> -        .parent         = TYPE_DEVICE,
> +        .parent         = TYPE_SYS_BUS_DEVICE,
>          .instance_size  = sizeof(RP2040State),
>          .instance_init  = rp2040_init,
>          .class_size     = sizeof(RP2040Class),

Squash that in patch #1 without any MemoryRegion property?