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Re: [PATCH 1/2] accel/tcg: Optimize jump cache flush during tlb range fl
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From: |
Idan Horowitz |
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Subject: |
Re: [PATCH 1/2] accel/tcg: Optimize jump cache flush during tlb range flush |
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Date: |
Fri, 14 Jan 2022 22:56:46 +0200 |
Idan Horowitz <idan.horowitz@gmail.com> wrote:
>
> cbnz x9, 0x5168abc8
>
I forgot to include the addresses of the instructions, making this
jump undecipherable, here's the snippet again but with addresses this
time:
0x5168abb0 movk x0, #0x0
0x5168abb4 movk x0, #0x0, lsl #16
0x5168abb8 movk x0, #0xff80, lsl #32
0x5168abbc movk x0, #0x0, lsl #48
0x5168abc0 mov x9, #0x64
0x5168abc4 str x9, [x8]
0x5168abc8 tlbi rvae1, x0
0x5168abcc ldr x9, [x8]
0x5168abd0 sub x9, x9, #0x1
0x5168abd4 str x9, [x8]
0x5168abd8 cbnz x9, 0x5168abc8
>
> Idan Horowitz
Idan Horowitz