Re: [PATCH v2 2/2] hw/arm/aspeed_ast2600: create i3c instance

[Troy Lee]

On Mon, Jan 10, 2022 at 10:31 PM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 1/10/22 08:21, Troy Lee wrote:
> > This patch includes i3c instance in ast2600 soc.
> >
> > v2: Rebase to mainline QEMU
> >
> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> > ---
> >   hw/arm/aspeed_ast2600.c     | 19 ++++++++++++++++++-
> >   include/hw/arm/aspeed_soc.h |  3 +++
> >   2 files changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> > index e33483fb5d..36aa31601a 100644
> > --- a/hw/arm/aspeed_ast2600.c
> > +++ b/hw/arm/aspeed_ast2600.c
> > @@ -29,7 +29,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
> >       [ASPEED_DEV_PWM]       = 0x1E610000,
> >       [ASPEED_DEV_FMC]       = 0x1E620000,
> >       [ASPEED_DEV_SPI1]      = 0x1E630000,
> > -    [ASPEED_DEV_SPI2]      = 0x1E641000,
> > +    [ASPEED_DEV_SPI2]      = 0x1E631000,
>
> Indeed ! But this belongs to another patch fixing the value.
>

Oops, that should be in a different branch, I might accidentally pick
that into my working branch. dkodihal will send it separately.


> >       [ASPEED_DEV_EHCI1]     = 0x1E6A1000,
> >       [ASPEED_DEV_EHCI2]     = 0x1E6A3000,
> >       [ASPEED_DEV_MII1]      = 0x1E650000,
> > @@ -61,6 +61,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
> >       [ASPEED_DEV_UART1]     = 0x1E783000,
> >       [ASPEED_DEV_UART5]     = 0x1E784000,
> >       [ASPEED_DEV_VUART]     = 0x1E787000,
> > +    [ASPEED_DEV_I3C]       = 0x1E7A0000,
> >       [ASPEED_DEV_SDRAM]     = 0x80000000,
> >   };
> >
> > @@ -108,6 +109,7 @@ static const int aspeed_soc_ast2600_irqmap[] = {
> >       [ASPEED_DEV_ETH4]      = 33,
> >       [ASPEED_DEV_KCS]       = 138,   /* 138 -> 142 */
> >       [ASPEED_DEV_DP]        = 62,
> > +    [ASPEED_DEV_I3C]       = 102,   /* 102 -> 107 */
> >   };
> >
> >   static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
> > @@ -223,6 +225,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
> >
> >       snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
> >       object_initialize_child(obj, "hace", &s->hace, typename);
> > +
> > +    object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
> >   }
> >
> >   /*
> > @@ -523,6 +527,19 @@ static void aspeed_soc_ast2600_realize(DeviceState 
> > *dev, Error **errp)
> >       sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, 
> > sc->memmap[ASPEED_DEV_HACE]);
> >       sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
> >                          aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
> > +    /* I3C */
> > +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
> > +        return;
> > +    }
> > +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, 
> > sc->memmap[ASPEED_DEV_I3C]);
> > +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c), 0,
> > +                       aspeed_soc_get_irq(s, ASPEED_DEV_I3C));
>
> The controller device does not have an IRQ line.
>

Removed in v3.
Thanks for the review,
Troy Lee

> Thanks,
>
> C.
>
>
>
> > +    for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
> > +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> > +                                        sc->irqmap[ASPEED_DEV_I3C] + i);
> > +        /* The AST2600 I3C controller has one IRQ per bus. */
> > +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
> > +    }
> >   }
> >
> >   static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index 18fb7eed46..cae9906684 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -21,6 +21,7 @@
> >   #include "hw/timer/aspeed_timer.h"
> >   #include "hw/rtc/aspeed_rtc.h"
> >   #include "hw/i2c/aspeed_i2c.h"
> > +#include "hw/misc/aspeed_i3c.h"
> >   #include "hw/ssi/aspeed_smc.h"
> >   #include "hw/misc/aspeed_hace.h"
> >   #include "hw/watchdog/wdt_aspeed.h"
> > @@ -51,6 +52,7 @@ struct AspeedSoCState {
> >       AspeedRtcState rtc;
> >       AspeedTimerCtrlState timerctrl;
> >       AspeedI2CState i2c;
> > +    AspeedI3CState i3c;
> >       AspeedSCUState scu;
> >       AspeedHACEState hace;
> >       AspeedXDMAState xdma;
> > @@ -141,6 +143,7 @@ enum {
> >       ASPEED_DEV_HACE,
> >       ASPEED_DEV_DPMCU,
> >       ASPEED_DEV_DP,
> > +    ASPEED_DEV_I3C,
> >   };
> >
> >   #endif /* ASPEED_SOC_H */
> >
>