Re: DSB does not seem to wait for TLBI completion

[Peter Maydell]

On Thu, 18 Nov 2021 at 15:46, Idan Horowitz <idan.horowitz@gmail.com> wrote:
>
> Hey, I'm running a bare-metal image on QEMU 6.1 and I've encountered the 
> following scenario:
> After receiving a data abort and mapping in the correct page I try to 
> invalidate the corresponding TLB entry using the following assembly sequence:
>
> dsb ish
> tlbi vaae1is, x0
> dsb sy

Do you have a repro case you can give us ?
Does your setup involve SMP, or is this all on a single CPU ?

> Unfortunately this does not seem to have any immediate effect, as upon 
> returning back to the source of the exception I immediately hit the same Data 
> Abort. This cycle of receiving a Data Abort and then updating the mapping 
> continues for 100s of times, until the TLB finally updates to the correct 
> mapping.

Note that the architecture says that the DSB will guarantee the
TLB maintenance operation to be finished for *other* processors,
but that if you want to guarantee it to be finished for the
processor which executed the TLBI then you must do a DSB followed
by a "context synchronization event", eg a ISB insn, or return
from exception. (See the v8 Arm ARM DDI0487G.b page D5-2833.)
It sounds from your description as if a return-from-exception
is done on the CPU that executed the TLBI, though...

-- PMM