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another gnucap-modelgen-verilog snapshot
From: |
Felix Salfelder |
Subject: |
another gnucap-modelgen-verilog snapshot |
Date: |
Wed, 30 Aug 2023 11:29:10 +0200 |
Dear all,
Our model compiler [0] now covers the Verilog-AMS language features most
widely used in analog modelling. The source code is available here [1]
and works with the current gnucap development snapshot.
We have prioritised features required in models from the Qucs project
[2] as well as in certain semiconductor and mems compact models
circulating under opaque or unsuitable licenses. For better support and
coverage, please get in touch with models and/or tests that we are
allowed to modify and redistribute freely.
Currently, we support the following.
- continuous disciplines (incl. tolerances)
- integer and real parameters, defaults, ranges, aliases
- builtin functions abs, exp, ln, min, max, pow, sqrt etc.
- contribution statements, potential/flow/indirect/switching
- named branches & value retention
- filters: ddt, ddx, idt, slew.
- control structures, conditional, loops, switch, ternary op.
- analysis("static"/"ic") conditionals
- limiting $limit, $limexp (limited)
- $strobe
These features are considered for the next snapshot and are under
development.
- ground declaration
- port flow probes
- timers, cross events
- different variants of noise
Please feel free to suggest others, and provide use cases.
This work was funded through the NGI0 Entrust Fund [3].
Best wishes
felix
[0] http://gnucap.org/dokuwiki/doku.php/gnucap:projects:nlnet:verilogams
[1]
http://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/tag/?h=20230829-dev
[2]
https://github.com/Qucs/qucsator/commit/905de6cdab0e342b98e06d1f68e9f8fce7de615a
[3] https://nlnet.nl/project/Gnucap-VerilogAMS/
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