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Re: modelgen & veriloga
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From: |
al davis |
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Subject: |
Re: modelgen & veriloga |
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Date: |
Thu, 27 Feb 2020 00:38:55 -0500 |
On Tue, 25 Feb 2020 15:01:04 +0100
Vincent Pinon <address@hidden> wrote:
> So we would go for a "subcircuit" architecture, not trying to plug
> directly into matrix? I understand it is more generic & flexible, is it
> as efficient?
more efficient for complex models that can benefit from the flexibility,
less efficient for simple models that can't.
My intent has always been to allow both. In verilog, "module" implies
subcircuit representation, "macromodule" implies flat representation.