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Re: [Gnucap-devel] Hierarchical name ordering


From: a r
Subject: Re: [Gnucap-devel] Hierarchical name ordering
Date: Sat, 19 Jan 2008 19:40:15 +0000

On Jan 19, 2008 6:48 PM, al davis <address@hidden> wrote:
>
> > BTW, can you post a sample code that:
> > a) replaces a nested cell with a different one,
> > b) replaces an instance parameter of such a cell.
> >
> > From the documentation, it seems like this is a supported
> > feature of
> >
> > Gnucap but I could have never figured out how to do it in
> > practice.
>
> Can you explain?
>
> a) I don't think it works.  Replace a component inside a
> particular instantiation of a subckt with something else?
>
> b) I think you can accomplish what you want with named
> parameters.  Remember .. in gnucap, a "param" is a variable.
> It can be changed at any time.  In some other simulators it is
> a text pre-processor substitution.
>
> .subckt foo (a b)
> .param bob=10k
> R1 (a b) bob
> .ends
>
> X1 (1 2) foo bob=2k
> X2 (2 3) foo bob=bill
> X3 (3 0) foo
>
> .param bill=300
> .op
> .param bill=2k
> .op

What I would like to be able to do is:

X1 (1 2) foo bob=2k

.alter different subcircuit
X1 (1 2) bar bob=2k

.alter bob=5k
.param X1.bob=5k

.alter different X1.R1
X1.R1 (a b) resistor_model r=bob w=2u

.alter remove X1.R1
.delete X1.R1

Of course, syntax is not an issue. I recall seeing commands like
modify, merge and delete in the gnucap manual. Can I do something
similar with them?

If not - ignore it. Interactive mode is not "must have" feature for
me. There is plenty more important things: expressions, more analyses,
IO commands, veriloga and so on.

-r.




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