[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET engine, compilers and to
|
From: |
Klaus Treichel |
|
Subject: |
[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET engine, compilers and tools (pnet) branch, master, updated. f014508985e3b387f0d0cbf60b7ff4943aad88e8 |
|
Date: |
Thu, 08 Apr 2010 11:39:45 +0000 |
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "DotGNU Portable.NET engine, compilers and tools (pnet)".
The branch, master has been updated
via f014508985e3b387f0d0cbf60b7ff4943aad88e8 (commit)
from 9fa68a32bcd0895a2324b5a76ae90368931c7515 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
http://git.savannah.gnu.org/cgit/pnet.git/commit/?id=f014508985e3b387f0d0cbf60b7ff4943aad88e8
commit f014508985e3b387f0d0cbf60b7ff4943aad88e8
Author: Klaus Treichel <address@hidden>
Date: Thu Apr 8 13:39:29 2010 +0200
Add more vfp float support for arm.
diff --git a/ChangeLog b/ChangeLog
index 7a689de..a6627ce 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,14 @@
+2010-04-08 Klaus Treichel <address@hidden>
+
+ * engine/unroll_conv.c (COP_F2I, COP_F2IU): Add unroller support for
+ these cvm opcodes.
+
+ * engine/md_arm.h: Add support for converting 32 bit ints from and to
+ floatingpoint values. Add support for float array loads and stores.
+
+ * engine/arm_codegen.h: Add code generation macros for int to float
+ conversions any vice versa.
+
2010-04-07 Klaus Treichel <address@hidden>
* engine/cvm.h: Mark the no longer used opcode COP_CCTOR_ONCE unsused.
diff --git a/engine/arm_codegen.h b/engine/arm_codegen.h
index b918010..a3c8a82 100644
--- a/engine/arm_codegen.h
+++ b/engine/arm_codegen.h
@@ -1151,6 +1151,138 @@ extern arm_inst_ptr _arm_mov_reg_imm(arm_inst_ptr inst,
int reg, int value);
} while (0)
/*
+ * Convert from signed integer in a single precision register to a
+ * single precision floatingpoint value. FSITOS
+ */
+#define arm_cvt_si_single(inst, cond, dreg, sreg) \
+ do { \
+ int __cvt_sreg = (int)(sreg); \
+ int __cvt_dreg = (int)(dreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0eb800c0) | \
+ ((__cvt_dreg & 1) <<
22) | \
+ ((__cvt_dreg & 0x1e) <<
11) | \
+ ((ARMVFP_CSINGLE) << 8)
| \
+ ((__cvt_sreg & 1) << 5)
| \
+ ((__cvt_sreg & 0x1e) >>
1)); \
+ } while (0)
+
+/*
+ * Convert from signed integer in a single precision register to a
+ * double precision floatingpoint value. FSITOD
+ */
+#define arm_cvt_si_double(inst, cond, dreg, sreg) \
+ do { \
+ int __cvt_sreg = (int)(sreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0eb800c0) | \
+ ((dreg) << 12) | \
+ ((ARMVFP_CDOUBLE) << 8)
| \
+ ((__cvt_sreg & 1) << 5)
| \
+ ((__cvt_sreg & 0x1e) >>
1)); \
+ } while (0)
+
+/*
+ * Convert from unsigned integer in a single precision register to a
+ * single precision floatingpoint value. FUITOS
+ */
+#define arm_cvt_ui_single(inst, cond, dreg, sreg) \
+ do { \
+ int __cvt_sreg = (int)(sreg); \
+ int __cvt_dreg = (int)(dreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0eb80040) | \
+ ((__cvt_dreg & 1) <<
22) | \
+ ((__cvt_dreg & 0x1e) <<
11) | \
+ ((ARMVFP_CSINGLE) << 8)
| \
+ ((__cvt_sreg & 1) << 5)
| \
+ ((__cvt_sreg & 0x1e) >>
1)); \
+ } while (0)
+
+/*
+ * Convert from unsigned integer in a single precision register to a
+ * double precision floatingpoint value. FSITOD
+ */
+#define arm_cvt_ui_double(inst, cond, dreg, sreg) \
+ do { \
+ int __cvt_sreg = (int)(sreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0eb80040) | \
+ ((dreg) << 12) | \
+ ((ARMVFP_CDOUBLE) << 8)
| \
+ ((__cvt_sreg & 1) << 5)
| \
+ ((__cvt_sreg & 0x1e) >>
1)); \
+ } while (0)
+
+/*
+ * Convert from single precision to a signed integer in a single
+ * precision register. Set to_zero != 0 if the truncate rounding mode
+ * has to be used regardless of the settings in the control register.
+ * FTOSI(Z)S
+ */
+#define arm_cvt_single_si(inst, cond, dreg, sreg, to_zero) \
+ do { \
+ int __cvt_sreg = (int)(sreg); \
+ int __cvt_dreg = (int)(dreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0ebd0040) | \
+ ((__cvt_dreg & 1) <<
22) | \
+ ((__cvt_dreg & 0x1e) <<
11) | \
+ ((ARMVFP_CSINGLE) << 8)
| \
+ ((((to_zero) != 0) ? 1
: 0) << 7) | \
+ ((__cvt_sreg & 1) << 5)
| \
+ ((__cvt_sreg & 0x1e) >>
1)); \
+ } while (0)
+
+/*
+ * Convert from double precision to a signed integer in a single
+ * precision register. Set to_zero != 0 if the truncate rounding mode
+ * has to be used regardless of the settings in the control register.
+ * FTOSI(Z)D
+ */
+#define arm_cvt_double_si(inst, cond, dreg, sreg, to_zero) \
+ do { \
+ int __cvt_dreg = (int)(dreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0ebd0040) | \
+ ((__cvt_dreg & 1) <<
22) | \
+ ((__cvt_dreg & 0x1e) <<
11) | \
+ ((ARMVFP_CDOUBLE) << 8)
| \
+ ((((to_zero) != 0) ? 1
: 0) << 7) | \
+ (sreg)); \
+ } while (0)
+
+/*
+ * Convert from single precision to an unsigned integer in a single
+ * precision register. Set to_zero != 0 if the truncate rounding mode
+ * has to be used regardless of the settings in the control register.
+ * FTOUI(Z)S
+ */
+#define arm_cvt_single_ui(inst, cond, dreg, sreg, to_zero) \
+ do { \
+ int __cvt_sreg = (int)(sreg); \
+ int __cvt_dreg = (int)(dreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0ebc0040) | \
+ ((__cvt_dreg & 1) <<
22) | \
+ ((__cvt_dreg & 0x1e) <<
11) | \
+ ((ARMVFP_CSINGLE) << 8)
| \
+ ((((to_zero) != 0) ? 1
: 0) << 7) | \
+ ((__cvt_sreg & 1) << 5)
| \
+ ((__cvt_sreg & 0x1e) >>
1)); \
+ } while (0)
+
+/*
+ * Convert from double precision to an unsigned integer in a single
+ * precision register. Set to_zero != 0 if the truncate rounding mode
+ * has to be used regardless of the settings in the control register.
+ * FTOUI(Z)D
+ */
+#define arm_cvt_double_ui(inst, cond, dreg, sreg, to_zero) \
+ do { \
+ int __cvt_dreg = (int)(dreg); \
+ *(inst)++ = (arm_build_prefix((cond),
0x0ebc0040) | \
+ ((__cvt_dreg & 1) <<
22) | \
+ ((__cvt_dreg & 0x1e) <<
11) | \
+ ((ARMVFP_CDOUBLE) << 8)
| \
+ ((((to_zero) != 0) ? 1
: 0) << 7) | \
+ (sreg)); \
+ } while (0)
+
+/*
* Compare two floatingpoint values (nonsignaling) FCMPx.
*/
#define arm_cmpn_single_reg_reg(inst,cond,sreg1,sreg2) \
diff --git a/engine/md_arm.h b/engine/md_arm.h
index 1ad044c..ff4ddfe 100644
--- a/engine/md_arm.h
+++ b/engine/md_arm.h
@@ -504,6 +504,58 @@ typedef arm_inst_ptr md_inst_ptr;
#define md_reg_to_word_native_un(inst,reg) \
do { ; } while (0)
+#ifdef ARM_HAS_FLOAT
+
+/*
+ * Convert a signed 32 bit value in the general register to a native
+ * floating-point value an load it into the top fp register.
+ */
+#define md_conv_sword_32_float(inst,dreg,sreg) \
+ do { \
+ int __i32f_dreg = ((int)(dreg) &
~MD_FREG_MASK); \
+ int __i32f_sreg = (__i32f_dreg << 1); \
+ arm_load_reg_single((inst), ARM_CC_AL,
__i32f_sreg, (sreg)); \
+ arm_cvt_si_double((inst), ARM_CC_AL,
__i32f_dreg, __i32f_sreg); \
+ } while (0)
+
+/*
+ * Convert an unsigned 32 bit value in the general register to a native
+ * floating-point value an load it into the top fp register.
+ */
+#define md_conv_uword_32_float(inst,dreg,sreg) \
+ do { \
+ int __u32f_dreg = ((int)(dreg) &
~MD_FREG_MASK); \
+ int __u32f_sreg = (__u32f_dreg << 1); \
+ arm_load_reg_single((inst), ARM_CC_AL,
__u32f_sreg, (sreg)); \
+ arm_cvt_ui_double((inst), ARM_CC_AL,
__u32f_dreg, __u32f_sreg); \
+ } while (0)
+
+/*
+ * Convert a native floating-point value to a signed 32 bit value using the
+ * truncate (round to zero) rounding mode and store it in a general purpose
+ * register.
+ */
+#define md_conv_float_sword_32(inst,dreg,sreg) \
+ do { \
+ int __fi32_dreg = ((int)(sreg) &
~MD_FREG_MASK); \
+ int __fi32_sreg = (__fi32_dreg << 1); \
+ arm_cvt_double_si((inst), ARM_CC_AL,
__fi32_sreg, __fi32_dreg, 1); \
+ arm_store_reg_single((inst), ARM_CC_AL, (dreg),
__fi32_sreg); \
+ } while (0)
+
+/*
+ * Convert a native floating-point value to an unsigned 32 bit value using
+ * the truncate (round to zero) rounding mode and store it in a general
+ * purpose register.
+ */
+#define md_conv_float_uword_32(inst,dreg,sreg) \
+ do { \
+ int __fu32_dreg = ((int)(sreg) &
~MD_FREG_MASK); \
+ int __fu32_sreg = (__fu32_dreg << 1); \
+ arm_cvt_double_ui((inst), ARM_CC_AL,
__fu32_sreg, __fu32_dreg, 1); \
+ arm_store_reg_single((inst), ARM_CC_AL, (dreg),
__fu32_sreg); \
+ } while (0)
+
/*
* Truncate floating point values to 32-bit or 64-bit.
*/
@@ -512,6 +564,8 @@ typedef arm_inst_ptr md_inst_ptr;
#define md_reg_to_float_64(inst,reg) \
do { ; } while (0)
+#endif /* ARM_HAS_FLOAT */
+
/*
* Swap the top two items on the floating-point stack.
*/
@@ -796,6 +850,28 @@ md_inst_ptr _md_arm_cmp_float(md_inst_ptr inst, int dreg,
int sreg1,
#define md_load_memindex_ushort(inst,reg,basereg,indexreg,disp) \
arm_load_memindex_ushort((inst), (reg), (basereg),
(indexreg))
+#ifdef ARM_HAS_FLOAT
+
+/*
+ * Load a 32 bit floatingpoint value from an indexed array.
+ */
+#define md_load_memindex_float_32(inst,reg,basereg,indexreg,disp) \
+ do { \
+ int __lf32_dreg = ((int)(reg) & ~MD_FREG_MASK);
\
+ arm_load_memindex_single((inst), ARM_CC_AL,
__lf32_dreg, (basereg), (indexreg)); \
+ } while (0)
+
+/*
+ * Load a 64 bit floatingpoint value from an indexed array.
+ */
+#define md_load_memindex_float_64(inst,reg,basereg,indexreg,disp) \
+ do { \
+ int __lf64_dreg = ((int)(reg) & ~MD_FREG_MASK);
\
+ arm_load_memindex_double((inst), ARM_CC_AL,
__lf64_dreg, (basereg), (indexreg)); \
+ } while (0)
+
+#endif /* ARM_HAS_FLOAT */
+
/*
* Store a 32-bit word value into an indexed array.
*/
@@ -834,6 +910,28 @@ md_inst_ptr _md_arm_cmp_float(md_inst_ptr inst, int dreg,
int sreg1,
#ifdef ARM_HAS_FLOAT
+/*
+ * Store a 32 bit floatingpoint value into an indexed array.
+ */
+#define md_store_memindex_float_32(inst,reg,basereg,indexreg,disp) \
+ do { \
+ int __sf32_dreg = ((int)(reg) & ~MD_FREG_MASK);
\
+ arm_store_memindex_single((inst), ARM_CC_AL,
__sf32_dreg, (basereg), (indexreg)); \
+ } while (0)
+
+/*
+ * Store a 64 bit floatingpoint value into an indexed array.
+ */
+#define md_store_memindex_float_64(inst,reg,basereg,indexreg,disp) \
+ do { \
+ int __sf64_dreg = ((int)(reg) & ~MD_FREG_MASK);
\
+ arm_store_memindex_double((inst), ARM_CC_AL,
__sf64_dreg, (basereg), (indexreg)); \
+ } while (0)
+
+#endif /* ARM_HAS_FLOAT */
+
+#ifdef ARM_HAS_FLOAT
+
#define md_add_reg_reg_float(inst,reg,reg2) \
do { \
int __add_reg1 = ((int)(reg) & ~MD_FREG_MASK); \
diff --git a/engine/unroll_conv.c b/engine/unroll_conv.c
index ca69d47..ea1d35f 100644
--- a/engine/unroll_conv.c
+++ b/engine/unroll_conv.c
@@ -104,7 +104,7 @@ break;
case COP_L2F:
{
- /* Read a float32 value from a pointer */
+ /* Convert a signed long value to float */
UNROLL_START();
CheckFPFull(&unroll);
#ifdef IL_NATIVE_INT32
@@ -138,7 +138,7 @@ break;
case COP_LU2F:
{
- /* Read a float32 value from a pointer */
+ /* Convert an unsigned long value to float */
UNROLL_START();
CheckFPFull(&unroll);
#ifdef IL_NATIVE_INT32
@@ -168,6 +168,44 @@ break;
#endif /* md_conv_uword_64_float */
+#ifdef md_conv_float_sword_32
+
+case COP_F2I:
+{
+ /* Convert native float to signed 32 bit using truncate rounding mode */
+ UNROLL_START();
+ CheckFPFull(&unroll);
+ reg = GetTopFPRegister(&unroll);
+ reg2 = GetWordRegister(&unroll, 0);
+ md_conv_float_sword_32(unroll.out, reg2, reg);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg2, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_conv_float_sword_32 */
+
+#ifdef md_conv_float_uword_32
+
+case COP_F2IU:
+{
+ /* Convert native float to unsigned 32 bit using truncate rounding mode
*/
+ UNROLL_START();
+ CheckFPFull(&unroll);
+ reg = GetTopFPRegister(&unroll);
+ reg2 = GetWordRegister(&unroll, 0);
+ md_conv_float_uword_32(unroll.out, reg2, reg);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg2, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_conv_float_uword_32 */
+
case COP_F2F:
{
/* Truncate a floating point value to float32 */
-----------------------------------------------------------------------
Summary of changes:
ChangeLog | 11 ++++
engine/arm_codegen.h | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
engine/md_arm.h | 98 +++++++++++++++++++++++++++++++++++++
engine/unroll_conv.c | 42 +++++++++++++++-
4 files changed, 281 insertions(+), 2 deletions(-)
hooks/post-receive
--
DotGNU Portable.NET engine, compilers and tools (pnet)
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [dotgnu-pnet-commits] [SCM] DotGNU Portable.NET engine, compilers and tools (pnet) branch, master, updated. f014508985e3b387f0d0cbf60b7ff4943aad88e8,
Klaus Treichel <=
- Prev by Date:
[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET branch, master, updated. d2ad33930e696c709804e8b818dab1426d5bae9f
- Next by Date:
[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET engine, compilers and tools (pnet) branch, master, updated. 7dc2e4f65e13c251cee5fb28b0c0f70568fd90aa
- Previous by thread:
[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET branch, master, updated. d2ad33930e696c709804e8b818dab1426d5bae9f
- Next by thread:
[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET engine, compilers and tools (pnet) branch, master, updated. 7dc2e4f65e13c251cee5fb28b0c0f70568fd90aa
- Index(es):