[Savannah-register-public] [task #7229] Submission of shelley

[Julien Boucaron]

URL:
  <http://savannah.gnu.org/task/?7229>

                 Summary: Submission of shelley
                 Project: Savannah Administration
            Submitted by: boucaron
            Submitted on: Monday 08/20/2007 at 14:52
         Should Start On: Monday 08/20/2007 at 00:00
   Should be Finished on: Thursday 08/30/2007 at 00:00
                Category: Project Approval
                Priority: 5 - Normal
                  Status: None
                 Privacy: Public
        Percent Complete: 0%
             Assigned to: None
             Open/Closed: Open
         Discussion Lock: Any
                  Effort: 0.00

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Details:

A new project has been registered at Savannah 
This project account will remain inactive until a site admin approves or
discards the registration.


= Registration Administration =

While this item will be useful to track the registration process, *approving
or discarding the registration must be done using the specific Group
Administration
<https://savannah.gnu.org/siteadmin/groupedit.php?group_id=9465> page*,
accessible only to site administrators, effectively *logged as site
administrators* (superuser):

* Group Administration
<https://savannah.gnu.org/siteadmin/groupedit.php?group_id=9465>


= Registration Details =

* Name: *shelley*
* System Name:  *shelley*
* Type: non-GNU software & documentation
* License: GNU General Public License v2 or later

----

==== Description: ====
SHELLEY
(Software HardwarE Light Language Yep!) is an object oriented imperative
language able to describe in one source, both software (C++,Java style) and
hardware (Verilog,VHDL style). 

The core syntax of the language is basically C,C++,Java.

The Object Oriented aspect is deeply inspired from both C++ and Java, with a
"broader" multiple inheritance, some additional features such as "accessor"
"setter" "getter" to ease the work of the developper...

The Hardware Language is deeply based on Verilog syntax.

Support for parallel and vector extensions like HPFortran.

A "starting" working grammar is available here:
http://julien.boucaron.free.fr/shelley/

We hope to add more features such as:
_ introduce also a verification language (certainly inspired from PSL/Sugar)
for hardware (model-checking through Sat solver/BDD).
_ algorithms for high-level synthesis (Hardware)
_ code co-generation and co-verification
_ helping generation of software drivers for hardware accelerators




==== Other Software Required: ====
jdk 1.5
antlr v3.0







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