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[PATCH v5 20/37] bsd-user/arm/target_arch_cpu.h: Implement data abort ex
From: |
Warner Losh |
Subject: |
[PATCH v5 20/37] bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions |
Date: |
Sun, 7 Nov 2021 20:51:19 -0700 |
Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data
exceptions cause a SIGSEGV.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Signed-off-by: Olivier Houchard <cognet@ci0.org>
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/arm/target_arch_cpu.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index 9f9b380b13..905a5ffaff 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -65,6 +65,17 @@ static inline void target_cpu_loop(CPUARMState *env)
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
+ case EXCP_PREFETCH_ABORT:
+ /* See arm/arm/trap.c prefetch_abort_handler() */
+ case EXCP_DATA_ABORT:
+ /* See arm/arm/trap.c data_abort_handler() */
+ info.si_signo = TARGET_SIGSEGV;
+ info.si_errno = 0;
+ /* XXX: check env->error_code */
+ info.si_code = 0;
+ info.si_addr = env->exception.vaddress;
+ queue_signal(env, info.si_signo, &info);
+ break;
case EXCP_DEBUG:
{
--
2.33.0
- Re: [PATCH v5 34/37] bsd-user/arm/signal.c: arm set_mcontext, (continued)
- [PATCH v5 15/37] bsd-user/arm/target_arch_cpu.c: Target specific TLS routines, Warner Losh, 2021/11/07
- [PATCH v5 36/37] bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE, Warner Losh, 2021/11/07
- [PATCH v5 29/37] bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack, Warner Losh, 2021/11/07
- [PATCH v5 32/37] bsd-user/arm/signal.c: arm set_sigtramp_args, Warner Losh, 2021/11/07
- [PATCH v5 21/37] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch, Warner Losh, 2021/11/07
- [PATCH v5 22/37] bsd-user/arm/target_arch_reg.h: Implement core dump register copying, Warner Losh, 2021/11/07
- [PATCH v5 18/37] bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation, Warner Losh, 2021/11/07
- [PATCH v5 31/37] bsd-user/arm/target_arch_signal.h: Define size of *context_t, Warner Losh, 2021/11/07
- [PATCH v5 37/37] bsd-user: add arm target build, Warner Losh, 2021/11/07
- [PATCH v5 20/37] bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions,
Warner Losh <=
- [PATCH v5 09/37] bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.h, Warner Losh, 2021/11/07
- [PATCH v5 23/37] bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space, Warner Losh, 2021/11/07