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Re: [PATCH v3] hw/adc/stm32f2xx_adc: Correct memory region size and acce
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v3] hw/adc/stm32f2xx_adc: Correct memory region size and access size |
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Date: |
Fri, 5 Jun 2020 14:29:24 +0100 |
On Wed, 3 Jun 2020 at 06:59, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The ADC region size is 256B, split as:
> - [0x00 - 0x4f] defined
> - [0x50 - 0xff] reserved
>
> All registers are 32-bit (thus when the datasheet mentions the
> last defined register is 0x4c, it means its address range is
> 0x4c .. 0x4f.
>
> This model implementation is also 32-bit. Set MemoryRegionOps
> 'impl' fields.
>
> See:
> 'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
>
> Reported-by: Seth Kintigh <skintigh@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Applied to target-arm.next, thanks.
-- PMM