Re: [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation

[Alistair Francis]

On Sun, Dec 22, 2024 at 6:40 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 29.10.2024 11:53, Yong-Xuan Wang wrote:
> > In the section "4.7 Precise effects on interrupt-pending bits"
> > of the RISC-V AIA specification defines that:
> >
> > "If the source mode is Level1 or Level0 and the interrupt domain
> > is configured in MSI delivery mode (domaincfg.DM = 1):
> > The pending bit is cleared whenever the rectified input value is
> > low, when the interrupt is forwarded by MSI, or by a relevant
> > write to an in_clrip register or to clripnum."
> >
> > Update the riscv_aplic_set_pending() to match the spec.
> >
> > Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation 
> > for APLIC MSI-mode")
>
> Is it a qemu-stable material?

Yes, I think it should be

Alistair

>
> Thanks,
>
> /mjt
>