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Re: [PATCH 3/3] target/arm: implement SEL2 physical and virtual timers
From: |
Alex Bennée |
Subject: |
Re: [PATCH 3/3] target/arm: implement SEL2 physical and virtual timers |
Date: |
Wed, 18 Dec 2024 17:07:53 +0000 |
User-agent: |
mu4e 1.12.7; emacs 29.4 |
Peter Maydell <peter.maydell@linaro.org> writes:
> On Fri, 6 Dec 2024 at 16:02, Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>> When FEAT_SEL2 was implemented the SEL2 timers where missed. This
>> shows up when building the latest Hafnium with SPMC_AT_EL=2. The
>> actual implementation utilises the same logic as the rest of the
>> timers so all we need to do is:
>>
>> - define the timers and their access functions
>> - conditionally add the correct system registers
>> - create a new accessfn as the rules are subtly different to the
>> existing secure timer
>
>> diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
>> index 8eaab603c0..b4ecca1b1c 100644
>> --- a/include/hw/arm/bsa.h
>> +++ b/include/hw/arm/bsa.h
>> @@ -22,6 +22,8 @@
>> #define QEMU_ARM_BSA_H
>>
>> /* These are architectural INTID values */
>> +#define ARCH_TIMER_S_VIRT_EL2_IRQ 19
>
> Can we call this ARM_TIMER_S_EL2_VIRT_IRQ please?
I'm going to assume you mean ARCH_TIMER_S_EL2_VIRT_IRQ ;-)
> We currently have ARCH_TIMER_NS_EL2_VIRT_IRQ
> so we should be consistent about where in
> the name we put the "VIRT" bit.
>
>> +#define ARCH_TIMER_S_EL2_IRQ 20
>> #define VIRTUAL_PMU_IRQ 23
>> #define ARCH_GIC_MAINT_IRQ 25
>> #define ARCH_TIMER_NS_EL2_IRQ 26
>
> -- PMM
--
Alex Bennée
Virtualisation Tech Lead @ Linaro