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[PATCH v3 2/2] hvf: arm: Handle unknown ID registers as RES0
From: |
Alexander Graf |
Subject: |
[PATCH v3 2/2] hvf: arm: Handle unknown ID registers as RES0 |
Date: |
Wed, 9 Feb 2022 13:41:35 +0100 |
Recent Linux versions added support to read ID_AA64ISAR2_EL1. On M1,
those reads trap into QEMU which handles them as faults.
However, AArch64 ID registers should always read as RES0. Let's
handle them accordingly.
This fixes booting Linux 5.17 guests.
Cc: qemu-stable@nongnu.org
Reported-by: Ivan Babrou <ivan@cloudflare.com>
Signed-off-by: Alexander Graf <agraf@csgraf.de>
---
v1 -> v2:
- Handle all ID registers instead of just ID_AA64ISAR2_EL1.
v2 -> v3:
- Use new sysreg parsing macros
- Remove useless check for op2
---
target/arm/hvf/hvf.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 8d0447ab01..5ca7aa2dcd 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -754,6 +754,15 @@ static bool hvf_handle_psci_call(CPUState *cpu)
return true;
}
+static bool is_id_sysreg(uint32_t reg)
+{
+ return SYSREG_OP0(reg) == 3 &&
+ SYSREG_OP1(reg) == 0 &&
+ SYSREG_CRN(reg) == 0 &&
+ SYSREG_CRM(reg) >= 1 &&
+ SYSREG_CRM(reg) < 8;
+}
+
static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -806,6 +815,11 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg,
uint32_t rt)
/* Dummy register */
break;
default:
+ if (is_id_sysreg(reg)) {
+ /* ID system registers read as RES0 */
+ val = 0;
+ break;
+ }
cpu_synchronize_state(cpu);
trace_hvf_unhandled_sysreg_read(env->pc, reg,
SYSREG_OP0(reg),
--
2.32.0 (Apple Git-132)
- [PATCH v3 2/2] hvf: arm: Handle unknown ID registers as RES0,
Alexander Graf <=