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Re: [PATCH v2 3/6] hw/sd: sdhci: Correctly set the controller status for
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v2 3/6] hw/sd: sdhci: Correctly set the controller status for ADMA |
Date: |
Thu, 18 Feb 2021 17:50:49 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 |
On 2/16/21 4:46 AM, Bin Meng wrote:
> When an ADMA transfer is started, the codes forget to set the
> controller status to indicate a transfer is in progress.
>
> With this fix, the following 2 reproducers:
>
> https://paste.debian.net/plain/1185136
> https://paste.debian.net/plain/1185141
>
> cannot be reproduced with the following QEMU command line:
>
> $ qemu-system-x86_64 -nographic -machine accel=qtest -m 512M \
> -nodefaults -device sdhci-pci,sd-spec-version=3 \
> -drive if=sd,index=0,file=null-co://,format=raw,id=mydrive \
> -device sd-card,drive=mydrive -qtest stdio
>
> Cc: qemu-stable@nongnu.org
> Fixes: CVE-2020-17380
> Fixes: CVE-2020-25085
> Fixes: CVE-2021-3409
> Fixes: d7dfca0807a0 ("hw/sdhci: introduce standard SD host controller")
> Reported-by: Alexander Bulekov <alxndr@bu.edu>
> Reported-by: Cornelius Aschermann (Ruhr-University Bochum)
> Reported-by: Muhammad Ramdhan
> Reported-by: Sergej Schumilo (Ruhr-University Bochum)
> Reported-by: Simon Wrner (Ruhr-University Bochum)
> Buglink: https://bugs.launchpad.net/qemu/+bug/1892960
> Buglink: https://bugs.launchpad.net/qemu/+bug/1909418
> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1928146
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> (no changes since v1)
>
> hw/sd/sdhci.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 05cb281..0b0ca6f 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -769,7 +769,9 @@ static void sdhci_do_adma(SDHCIState *s)
>
> switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
> case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
> + s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE;
> if (s->trnmod & SDHC_TRNS_READ) {
> + s->prnsts |= SDHC_DOING_READ;
> while (length) {
> if (s->data_count == 0) {
> sdbus_read_data(&s->sdbus, s->fifo_buffer,
> block_size);
> @@ -797,6 +799,7 @@ static void sdhci_do_adma(SDHCIState *s)
> }
> }
> } else {
> + s->prnsts |= SDHC_DOING_WRITE;
> while (length) {
> begin = s->data_count;
> if ((length + begin) < block_size) {
Nice fix.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
- [PATCH v2 0/6] hw/sd: sdhci: Fixes to CVE-2020-17380, CVE-2020-25085, CVE-2021-3409, Bin Meng, 2021/02/15
- [PATCH v2 1/6] hw/sd: sdhci: Don't transfer any data when command time out, Bin Meng, 2021/02/15
- [PATCH v2 2/6] hw/sd: sdhci: Don't write to SDHC_SYSAD register when transfer is in progress, Bin Meng, 2021/02/15
- [PATCH v2 3/6] hw/sd: sdhci: Correctly set the controller status for ADMA, Bin Meng, 2021/02/15
- Re: [PATCH v2 3/6] hw/sd: sdhci: Correctly set the controller status for ADMA,
Philippe Mathieu-Daudé <=
- [PATCH v2 4/6] hw/sd: sdhci: Simplify updating s->prnsts in sdhci_sdma_transfer_multi_blocks(), Bin Meng, 2021/02/15
- [PATCH v2 5/6] hw/sd: sdhci: Limit block size only when SDHC_BLKSIZE register is writable, Bin Meng, 2021/02/15
- [PATCH v2 6/6] hw/sd: sdhci: Reset the data pointer of s->fifo_buffer[] when a different block size is programmed, Bin Meng, 2021/02/15