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[Qemu-stable] [PATCH 65/99] softfloat: Handle default NaN mode after pic
From: |
Michael Roth |
Subject: |
[Qemu-stable] [PATCH 65/99] softfloat: Handle default NaN mode after pickNaNMulAdd, not before |
Date: |
Mon, 23 Jul 2018 15:17:14 -0500 |
From: Peter Maydell <address@hidden>
It is implementation defined whether a multiply-add of
(0,inf,qnan) or (inf,0,qnan) raises InvalidaOperation or
not, so we let the target-specific pickNaNMulAdd function
handle this. This means that we must do the "return the
default NaN in default NaN mode" check after the call,
not before. Correct the ordering, and restore the comment
from the old propagateFloat64MulAddNaN() that warned about
this corner case.
This fixes a regression from 2.11 for Arm guests where we would
incorrectly fail to set the Invalid flag for these cases.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
(cherry picked from commit 1839189bbf89889076aadf0c793c1b57977b28d7)
Signed-off-by: Michael Roth <address@hidden>
---
fpu/softfloat.c | 48 ++++++++++++++++++++++++++++--------------------
1 file changed, 28 insertions(+), 20 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 70e0c40a1c..8401b37bd4 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -602,34 +602,42 @@ static FloatParts pick_nan(FloatParts a, FloatParts b,
float_status *s)
static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c,
bool inf_zero, float_status *s)
{
+ int which;
+
if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) {
s->float_exception_flags |= float_flag_invalid;
}
+ which = pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls),
+ is_qnan(b.cls), is_snan(b.cls),
+ is_qnan(c.cls), is_snan(c.cls),
+ inf_zero, s);
+
if (s->default_nan_mode) {
+ /* Note that this check is after pickNaNMulAdd so that function
+ * has an opportunity to set the Invalid flag.
+ */
a.cls = float_class_dnan;
- } else {
- switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls),
- is_qnan(b.cls), is_snan(b.cls),
- is_qnan(c.cls), is_snan(c.cls),
- inf_zero, s)) {
- case 0:
- break;
- case 1:
- a = b;
- break;
- case 2:
- a = c;
- break;
- case 3:
- a.cls = float_class_dnan;
- return a;
- default:
- g_assert_not_reached();
- }
+ return a;
+ }
- a.cls = float_class_msnan;
+ switch (which) {
+ case 0:
+ break;
+ case 1:
+ a = b;
+ break;
+ case 2:
+ a = c;
+ break;
+ case 3:
+ a.cls = float_class_dnan;
+ return a;
+ default:
+ g_assert_not_reached();
}
+ a.cls = float_class_msnan;
+
return a;
}
--
2.17.1
- [Qemu-stable] [PATCH 05/99] s390-ccw: force diag 308 subcode to unsigned long, (continued)
[Qemu-stable] [PATCH 59/99] iotests: Add test for cancelling a mirror job, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 61/99] riscv: htif: increase the priority of the htif subregion, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 62/99] riscv: requires libfdt, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 63/99] nbd/client: Relax handling of large NBD_CMD_BLOCK_STATUS reply, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 64/99] tcg/i386: Fix dup_vec in non-AVX2 codepath, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 65/99] softfloat: Handle default NaN mode after pickNaNMulAdd, not before,
Michael Roth <=
[Qemu-stable] [PATCH 66/99] tcg: Limit the number of ops in a TB, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 67/99] RISC-V: Minimal QEMU 2.12 fix for sifive_u machine, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 69/99] target/arm: Fix fp_status_f16 tininess before rounding, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 68/99] blockjob: expose error string via query, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 70/99] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 06/99] tcg/arm: Fix memory barrier encoding, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 71/99] target/arm: Implement vector shifted SCVF/UCVF for fp16, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 72/99] target/arm: Implement vector shifted FCVT for fp16, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 73/99] target/arm: Fix float16 to/from int16, Michael Roth, 2018/07/23
[Qemu-stable] [PATCH 74/99] target/arm: Clear SVE high bits for FMOV, Michael Roth, 2018/07/23