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Re: [Qemu-stable] [Qemu-devel] [PATCH] target-arm: Make reserved ranges
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-stable] [Qemu-devel] [PATCH] target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF |
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Date: |
Thu, 25 Feb 2016 16:48:36 +0000 |
Ping? (less than a week, I know, but given it unbreaks linux-next
I figure it would be nicer to get it into master sooner rather
than later...)
thanks
-- PMM
On 19 February 2016 at 14:07, Peter Maydell <address@hidden> wrote:
> The v8 ARM ARM defines that unused spaces in the ID_AA64* system
> register ranges are Reserved and must RAZ, rather than being UNDEF.
> Implement this.
>
> In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2,
> and newer versions of the Linux kernel will attempt to read this,
> which causes them not to boot up on versions of QEMU missing this fix.
>
> Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6
> is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in
> the ARMCPU struct so CPUs can override it, though since none do
> this too will just RAZ.
>
> Cc: address@hidden
> Reported-by: Ard Biesheuvel <address@hidden>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> The patch which touches ID_AA64MMFR2 is currently in linux-next...
>
> target-arm/cpu-qom.h | 1 +
> target-arm/helper.c | 128
> ++++++++++++++++++++++++++++++++++++++++++++++++---
> 2 files changed, 122 insertions(+), 7 deletions(-)
>
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> index 1cc4502..1061c08 100644
> --- a/target-arm/cpu-qom.h
> +++ b/target-arm/cpu-qom.h
> @@ -155,6 +155,7 @@ typedef struct ARMCPU {
> uint32_t id_mmfr1;
> uint32_t id_mmfr2;
> uint32_t id_mmfr3;
> + uint32_t id_mmfr4;
> uint32_t id_isar0;
> uint32_t id_isar1;
> uint32_t id_isar2;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 5a0447b..4deea0f 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4280,12 +4280,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_isar5 },
> - /* 6..7 are as yet unallocated and must RAZ */
> - { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
> - .resetvalue = 0 },
> - { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
> - .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
> + { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->id_mmfr4 },
> + /* 7 is as yet unallocated and must RAZ */
> + { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = 0 },
> REGINFO_SENTINEL
> };
> @@ -4339,7 +4341,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> define_arm_cp_regs(cpu, not_v7_cp_reginfo);
> }
> if (arm_feature(env, ARM_FEATURE_V8)) {
> - /* AArch64 ID registers, which all have impdef reset values */
> + /* AArch64 ID registers, which all have impdef reset values.
> + * Note that within the ID register ranges the unused slots
> + * must all RAZ, not UNDEF; future architecture versions may
> + * define new registers here.
> + */
> ARMCPRegInfo v8_idregs[] = {
> { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
> @@ -4349,6 +4355,30 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_aa64pfr1},
> + { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -4362,6 +4392,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_aa64dfr1 },
> + { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -4370,6 +4408,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_aa64afr1 },
> + { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -4378,6 +4424,30 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_aa64isar1 },
> + { .name = "ID_AA64ISAR2_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64ISAR3_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64ISAR4_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64ISAR5_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64ISAR6_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64ISAR7_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -4386,6 +4456,30 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_aa64mmfr1 },
> + { .name = "ID_AA64MMFR2_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64MMFR3_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64MMFR4_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64MMFR5_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64MMFR6_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "ID_AA64MMFR7_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -4398,6 +4492,26 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->mvfr2 },
> + { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> + { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = 0 },
> { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
> .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
> .access = PL0_R, .accessfn = pmreg_access, .type =
> ARM_CP_CONST,
> --
> 1.9.1