[Qemu-stable] [PULL 4/5] target-ppc: Move the FPSCR bit update macros to cpu.h

[David Gibson]

From: Madhavan Srinivasan <address@hidden>

Move the FPSCR bit update macros defined in dfp_helper
to cpu.h. This way, fpu_helper functions can also use them

Signed-off-by: Madhavan Srinivasan <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
 target-ppc/cpu.h        | 21 +++++++++++++++++++++
 target-ppc/dfp_helper.c | 21 ---------------------
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 31c6fee..9706000 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -684,6 +684,27 @@ enum {
 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
                    0x1F)
 
+#define FP_FX          (1ull << FPSCR_FX)
+#define FP_FEX         (1ull << FPSCR_FEX)
+#define FP_OX          (1ull << FPSCR_OX)
+#define FP_OE          (1ull << FPSCR_OE)
+#define FP_UX          (1ull << FPSCR_UX)
+#define FP_UE          (1ull << FPSCR_UE)
+#define FP_XX          (1ull << FPSCR_XX)
+#define FP_XE          (1ull << FPSCR_XE)
+#define FP_ZX          (1ull << FPSCR_ZX)
+#define FP_ZE          (1ull << FPSCR_ZE)
+#define FP_VX          (1ull << FPSCR_VX)
+#define FP_VXSNAN      (1ull << FPSCR_VXSNAN)
+#define FP_VXISI       (1ull << FPSCR_VXISI)
+#define FP_VXIMZ       (1ull << FPSCR_VXIMZ)
+#define FP_VXZDZ       (1ull << FPSCR_VXZDZ)
+#define FP_VXIDI       (1ull << FPSCR_VXIDI)
+#define FP_VXVC                (1ull << FPSCR_VXVC)
+#define FP_VXCVI       (1ull << FPSCR_VXCVI)
+#define FP_VE          (1ull << FPSCR_VE)
+#define FP_FI          (1ull << FPSCR_FI)
+
 /*****************************************************************************/
 /* Vector status and control register */
 #define VSCR_NJ                16 /* Vector non-java */
diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index 49820bf..451e434 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -170,27 +170,6 @@ static void dfp_prepare_decimal128(struct PPC_DFP *dfp, 
uint64_t *a,
     }
 }
 
-#define FP_FX       (1ull << FPSCR_FX)
-#define FP_FEX      (1ull << FPSCR_FEX)
-#define FP_OX       (1ull << FPSCR_OX)
-#define FP_OE       (1ull << FPSCR_OE)
-#define FP_UX       (1ull << FPSCR_UX)
-#define FP_UE       (1ull << FPSCR_UE)
-#define FP_XX       (1ull << FPSCR_XX)
-#define FP_XE       (1ull << FPSCR_XE)
-#define FP_ZX       (1ull << FPSCR_ZX)
-#define FP_ZE       (1ull << FPSCR_ZE)
-#define FP_VX       (1ull << FPSCR_VX)
-#define FP_VXSNAN   (1ull << FPSCR_VXSNAN)
-#define FP_VXISI    (1ull << FPSCR_VXISI)
-#define FP_VXIMZ    (1ull << FPSCR_VXIMZ)
-#define FP_VXZDZ    (1ull << FPSCR_VXZDZ)
-#define FP_VXIDI    (1ull << FPSCR_VXIDI)
-#define FP_VXVC     (1ull << FPSCR_VXVC)
-#define FP_VXCVI    (1ull << FPSCR_VXCVI)
-#define FP_VE       (1ull << FPSCR_VE)
-#define FP_FI       (1ull << FPSCR_FI)
-
 static void dfp_set_FPSCR_flag(struct PPC_DFP *dfp, uint64_t flag,
                 uint64_t enabled)
 {
-- 
2.5.0