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[PULL 10/60] target/arm: Move internal declarations from 'cpu-qom.h' to
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 10/60] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h' |
Date: |
Mon, 6 Nov 2023 12:02:42 +0100 |
These definitions and declarations are only used by
target/arm/, no need to expose them to generic hw/.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-4-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <c48c9829-3dfa-79cf-3042-454fda0d00dc@linaro.org>
---
target/arm/cpu-qom.h | 28 ----------------------------
target/arm/cpu.h | 22 ++++++++++++++++++++++
target/arm/internals.h | 6 ++++++
3 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index dfb9d5b827..35c3b0924e 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -35,9 +35,6 @@ typedef struct ARMCPUInfo {
void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
-void arm_cpu_register(const ARMCPUInfo *info);
-void aarch64_cpu_register(const ARMCPUInfo *info);
-
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
@@ -63,29 +60,4 @@ struct AArch64CPUClass {
ARMCPUClass parent_class;
};
-void register_cp_regs_for_features(ARMCPU *cpu);
-void init_cpreg_list(ARMCPU *cpu);
-
-/* Callback functions for the generic timer's timers. */
-void arm_gt_ptimer_cb(void *opaque);
-void arm_gt_vtimer_cb(void *opaque);
-void arm_gt_htimer_cb(void *opaque);
-void arm_gt_stimer_cb(void *opaque);
-void arm_gt_hvtimer_cb(void *opaque);
-
-#define ARM_AFF0_SHIFT 0
-#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
-#define ARM_AFF1_SHIFT 8
-#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
-#define ARM_AFF2_SHIFT 16
-#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
-#define ARM_AFF3_SHIFT 32
-#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
-#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
-
-#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
-#define ARM64_AFFINITY_MASK \
- (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
-#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
-
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2f7ab22169..4a86c8f831 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1116,11 +1116,33 @@ struct ArchCPU {
uint64_t gt_cntfrq_hz;
};
+/* Callback functions for the generic timer's timers. */
+void arm_gt_ptimer_cb(void *opaque);
+void arm_gt_vtimer_cb(void *opaque);
+void arm_gt_htimer_cb(void *opaque);
+void arm_gt_stimer_cb(void *opaque);
+void arm_gt_hvtimer_cb(void *opaque);
+
unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
void arm_cpu_post_init(Object *obj);
+#define ARM_AFF0_SHIFT 0
+#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
+#define ARM_AFF1_SHIFT 8
+#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
+#define ARM_AFF2_SHIFT 16
+#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
+#define ARM_AFF3_SHIFT 32
+#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
+#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
+
+#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
+#define ARM64_AFFINITY_MASK \
+ (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
+#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
+
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
#ifndef CONFIG_USER_ONLY
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c837506e44..143d57c0fe 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -183,6 +183,12 @@ static inline int r14_bank_number(int mode)
return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
}
+void arm_cpu_register(const ARMCPUInfo *info);
+void aarch64_cpu_register(const ARMCPUInfo *info);
+
+void register_cp_regs_for_features(ARMCPU *cpu);
+void init_cpreg_list(ARMCPU *cpu);
+
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);
--
2.41.0
- [PULL 00/60] Misc HW/UI patches for 2023-11-06, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 01/60] vl: Free machine list, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 02/60] vl: constify default_list, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 03/60] tests/vm/ubuntu.aarch64: Correct comment about TCG specific delay, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 04/60] tests/unit/test-seccomp: Remove mentions of softmmu in test names, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 05/60] accel/tcg: Declare tcg_flush_jmp_cache() in 'exec/tb-flush.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 06/60] accel: Introduce cpu_exec_reset_hold(), Philippe Mathieu-Daudé, 2023/11/06
- [PULL 07/60] accel/tcg: Factor tcg_cpu_reset_hold() out, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 09/60] target: Mention 'cpu-qom.h' is target agnostic, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 08/60] target: Unify QOM style, Philippe Mathieu-Daudé, 2023/11/06
- [PULL 10/60] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h',
Philippe Mathieu-Daudé <=
- [PULL 12/60] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 11/60] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 13/60] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 14/60] target/hexagon: Declare QOM definitions in 'cpu-qom.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 15/60] target/loongarch: Declare QOM definitions in 'cpu-qom.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 16/60] target/nios2: Declare QOM definitions in 'cpu-qom.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 17/60] target/openrisc: Declare QOM definitions in 'cpu-qom.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 18/60] target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h', Philippe Mathieu-Daudé, 2023/11/06
- [PULL 19/60] target/ppc: Use env_archcpu() in helper_book3s_msgsndp(), Philippe Mathieu-Daudé, 2023/11/06
- [PULL 20/60] target/riscv: Use env_archcpu() in [check_]nanbox(), Philippe Mathieu-Daudé, 2023/11/06