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[PATCH v5 44/54] tcg/mips: Use atom_and_align_for_opc
From: |
Richard Henderson |
Subject: |
[PATCH v5 44/54] tcg/mips: Use atom_and_align_for_opc |
Date: |
Mon, 15 May 2023 07:33:03 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index cd0254a0d7..3f3fe5b991 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1138,7 +1138,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
typedef struct {
TCGReg base;
- MemOp align;
+ TCGAtomAlign aa;
} HostAddress;
bool tcg_target_has_memory_bswap(MemOp memop)
@@ -1158,11 +1158,15 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext
*s, HostAddress *h,
{
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
- unsigned a_bits = get_alignment_bits(opc);
+ MemOp a_bits;
unsigned s_bits = opc & MO_SIZE;
- unsigned a_mask = (1 << a_bits) - 1;
+ unsigned a_mask;
TCGReg base;
+ h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
+ a_bits = h->aa.align;
+ a_mask = (1 << a_bits) - 1;
+
#ifdef CONFIG_SOFTMMU
unsigned s_mask = (1 << s_bits) - 1;
int mem_index = get_mmuidx(oi);
@@ -1281,7 +1285,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
#endif
h->base = base;
- h->align = a_bits;
return ldst;
}
@@ -1394,7 +1397,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo,
TCGReg datahi,
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
- if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
+ if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
} else {
tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type);
@@ -1481,7 +1484,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo,
TCGReg datahi,
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
- if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
+ if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
} else {
tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
--
2.34.1
- [PATCH v5 31/54] tcg/loongarch64: Check the host supports unaligned accesses, (continued)
- [PATCH v5 31/54] tcg/loongarch64: Check the host supports unaligned accesses, Richard Henderson, 2023/05/15
- [PATCH v5 35/54] tcg: Add INDEX_op_qemu_{ld,st}_i128, Richard Henderson, 2023/05/15
- [PATCH v5 34/54] tcg: Introduce tcg_target_has_memory_bswap, Richard Henderson, 2023/05/15
- [PATCH v5 30/54] accel/tcg: Remove helper_unaligned_{ld,st}, Richard Henderson, 2023/05/15
- [PATCH v5 42/54] tcg/arm: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 40/54] tcg/i386: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 43/54] tcg/loongarch64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 41/54] tcg/aarch64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 44/54] tcg/mips: Use atom_and_align_for_opc,
Richard Henderson <=
- [PATCH v5 45/54] tcg/ppc: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 50/54] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2023/05/15
- [PATCH v5 51/54] tcg/aarch64: Rename temporaries, Richard Henderson, 2023/05/15
- [PATCH v5 47/54] tcg/s390x: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 46/54] tcg/riscv: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 48/54] tcg/sparc64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 49/54] tcg/i386: Honor 64-bit atomicity in 32-bit mode, Richard Henderson, 2023/05/15