[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 24/54] tcg/sparc64: Allocate %g2 as a third temporary
From: |
Richard Henderson |
Subject: |
[PATCH v5 24/54] tcg/sparc64: Allocate %g2 as a third temporary |
Date: |
Mon, 15 May 2023 07:32:43 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc64/tcg-target.c.inc | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index e997db2645..64464ab363 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -83,9 +83,10 @@ static const char * const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
-/* Define some temporary registers. T2 is used for constant generation. */
+/* Define some temporary registers. T3 is used for constant generation. */
#define TCG_REG_T1 TCG_REG_G1
-#define TCG_REG_T2 TCG_REG_O7
+#define TCG_REG_T2 TCG_REG_G2
+#define TCG_REG_T3 TCG_REG_O7
#ifndef CONFIG_SOFTMMU
# define TCG_GUEST_BASE_REG TCG_REG_I5
@@ -110,7 +111,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_I4,
TCG_REG_I5,
- TCG_REG_G2,
TCG_REG_G3,
TCG_REG_G4,
TCG_REG_G5,
@@ -492,8 +492,8 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type,
TCGReg ret,
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
- tcg_debug_assert(ret != TCG_REG_T2);
- tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2);
+ tcg_debug_assert(ret != TCG_REG_T3);
+ tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3);
}
static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
@@ -885,10 +885,8 @@ static void tcg_out_jmpl_const(TCGContext *s, const
tcg_insn_unit *dest,
{
uintptr_t desti = (uintptr_t)dest;
- /* Be careful not to clobber %o7 for a tail call. */
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1,
- desti & ~0xfff, in_prologue,
- tail_call ? TCG_REG_G2 : TCG_REG_O7);
+ desti & ~0xfff, in_prologue, TCG_REG_T2);
tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7,
TCG_REG_T1, desti & 0xfff, JMPL);
}
@@ -1856,6 +1854,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */
}
#define ELF_HOST_MACHINE EM_SPARCV9
--
2.34.1
- Re: [PATCH v5 11/54] accel/tcg: Add aarch64 specific support in ldst_atomicity, (continued)
- [PATCH v5 13/54] tcg/aarch64: Detect have_lse, have_lse2 for darwin, Richard Henderson, 2023/05/15
- [PATCH v5 19/54] tcg/riscv: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 10/54] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc, Richard Henderson, 2023/05/15
- [PATCH v5 14/54] accel/tcg: Add have_lse2 support in ldst_atomicity, Richard Henderson, 2023/05/15
- [PATCH v5 16/54] tcg/aarch64: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 18/54] tcg/loongarch64: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 24/54] tcg/sparc64: Allocate %g2 as a third temporary,
Richard Henderson <=
- [PATCH v5 15/54] tcg/i386: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 22/54] tcg/mips: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 21/54] tcg/arm: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 25/54] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13, Richard Henderson, 2023/05/15
- [PATCH v5 36/54] tcg: Introduce tcg_out_movext3, Richard Henderson, 2023/05/15
- [PATCH v5 20/54] tcg/arm: Adjust constraints on qemu_ld/st, Richard Henderson, 2023/05/15