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Re: [PATCH v5 22/30] tcg/mips: Reorg tlb load within prepare_host_addr
From: |
Alex Bennée |
Subject: |
Re: [PATCH v5 22/30] tcg/mips: Reorg tlb load within prepare_host_addr |
Date: |
Wed, 10 May 2023 14:49:51 +0100 |
User-agent: |
mu4e 1.11.4; emacs 29.0.90 |
Richard Henderson <richard.henderson@linaro.org> writes:
> Compare the address vs the tlb entry with sign-extended values.
> This simplifies the page+alignment mask constant, and the
> generation of the last byte address for the misaligned test.
>
> Move the tlb addend load up, and the zero-extension down.
>
> This frees up a register, which allows us use TMP3 as the returned base
> address register instead of A0, which we were using as a 5th temporary.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
- Re: [PATCH v5 17/30] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path, (continued)
- [PATCH v5 19/30] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path, Richard Henderson, 2023/05/06
- [PATCH v5 18/30] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path, Richard Henderson, 2023/05/06
- [PATCH v5 20/30] tcg/loongarch64: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/05/06
- [PATCH v5 21/30] tcg/mips: Remove MO_BSWAP handling, Richard Henderson, 2023/05/06
- [PATCH v5 22/30] tcg/mips: Reorg tlb load within prepare_host_addr, Richard Henderson, 2023/05/06
- Re: [PATCH v5 22/30] tcg/mips: Reorg tlb load within prepare_host_addr,
Alex Bennée <=
- [PATCH v5 24/30] tcg/ppc: Reorg tcg_out_tlb_read, Richard Henderson, 2023/05/06
- [PATCH v5 26/30] tcg/ppc: Remove unused constraints A, B, C, D, Richard Henderson, 2023/05/06
- [PATCH v5 23/30] tcg/mips: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/05/06
- [PATCH v5 25/30] tcg/ppc: Adjust constraints on qemu_ld/st, Richard Henderson, 2023/05/06
- [PATCH v5 28/30] tcg/riscv: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/05/06