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Re: [PATCH v4 06/57] accel/tcg: Honor atomicity of loads
From: |
Peter Maydell |
Subject: |
Re: [PATCH v4 06/57] accel/tcg: Honor atomicity of loads |
Date: |
Tue, 9 May 2023 15:33:51 +0100 |
On Tue, 9 May 2023 at 15:27, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 5/9/23 13:04, Peter Maydell wrote:
> >> If the LDP is aligned mod 8, but not aligned mod 16, then both 8-byte
> >> operations must be
> >> (separately) atomic, and we return MO_64.
> >
> > So there's an implicit "at most 2 atomic sub-operations
> > inside a WITHIN16 load" restriction? i.e. you can't
> > use WITHIN16 to say "do this 8 byte load atomically but
> > if it's not in a 16-byte region do it with 4 2-byte loads",
> > even though in theory MO_ATOM_WITHIN16 | MO_ATMAX_2 | MO_8
> > would describe that ?
>
> Correct on both counts. While you're right that this is a valid
> generalization, it's not
> something for which I've found a use case.
Yeah, that's fine -- but we should note the restrictions/
requirements in the doc comment for WITHIN16. (And maybe
an assert somewhere if there's somewhere convenient to
put it?)
thanks
-- PMM
- Re: [PATCH v4 11/57] tcg/tci: Use helper_{ld,st}*_mmu for user-only, (continued)
[PATCH v4 08/57] target/loongarch: Do not include tcg-ldst.h, Richard Henderson, 2023/05/03
[PATCH v4 07/57] accel/tcg: Honor atomicity of stores, Richard Henderson, 2023/05/03
[PATCH v4 10/57] accel/tcg: Implement helper_{ld, st}*_mmu for user-only, Richard Henderson, 2023/05/03
[PATCH v4 14/57] tcg/i386: Add have_atomic16, Richard Henderson, 2023/05/03