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[PATCH 10/12] target/s390x: Handle STGRL to non-aligned addresses
From: |
Ilya Leoshkevich |
Subject: |
[PATCH 10/12] target/s390x: Handle STGRL to non-aligned addresses |
Date: |
Fri, 10 Mar 2023 18:42:21 +0100 |
Use MO_ALIGN_8 and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/s390x/tcg/insn-data.h.inc | 8 ++++----
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 4e635fb1677..c60e29b3ad9 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -842,14 +842,14 @@
/* STORE */
D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0)
D(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0, 0)
- C(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0)
- F(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, IF_AFP1)
- F(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, IF_AFP1)
+ D(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0, 0)
+ E(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
+ E(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
E(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
E(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
/* STORE RELATIVE LONG */
D(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0, MO_ALIGN_4)
- C(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0)
+ D(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0, MO_ALIGN_8)
/* STORE CHARACTER */
C(0x4200, STC, RX_a, Z, r1_o, a2, 0, 0, st8, 0)
C(0xe372, STCY, RXY_a, LD, r1_o, a2, 0, 0, st8, 0)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 818f3292c5c..5609ea2e93d 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -4504,7 +4504,8 @@ static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
static DisasJumpType op_st64(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s),
+ MO_TEUQ | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
- [PATCH 08/12] target/s390x: Handle CLRL and CLGFRL with non-aligned addresses, (continued)
- [PATCH 08/12] target/s390x: Handle CLRL and CLGFRL with non-aligned addresses, Ilya Leoshkevich, 2023/03/10
- [PATCH 06/12] target/s390x: Handle CRL and CGFRL with non-aligned addresses, Ilya Leoshkevich, 2023/03/10
- [PATCH 07/12] target/s390x: Handle CGRL and CLGRL with non-aligned addresses, Ilya Leoshkevich, 2023/03/10
- [PATCH 11/12] target/s390x: Update do_unaligned_access() comment, Ilya Leoshkevich, 2023/03/10
- [PATCH 09/12] target/s390x: Handle STRL to non-aligned addresses, Ilya Leoshkevich, 2023/03/10
- [PATCH 10/12] target/s390x: Handle STGRL to non-aligned addresses,
Ilya Leoshkevich <=
- [PATCH 12/12] tests/tcg/s390x: Test unaligned accesses, Ilya Leoshkevich, 2023/03/10