Re: [PATCH 45/70] target/riscv: Avoid tcg_const_*

[liweiwei]

On 2023/2/27 13:42, Richard Henderson wrote:
> All uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Weiwei Li

> ---
>   target/riscv/translate.c                  | 4 ++--
>   target/riscv/insn_trans/trans_rvv.c.inc   | 4 ++--
>   target/riscv/insn_trans/trans_rvzfh.c.inc | 2 +-
>   3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 180fa5d30d..5c558a6f5f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -201,8 +201,8 @@ static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
>    */
>   static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
>   {
> -    TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
> -    TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
> +    TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
> +    TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull);
>   
>       tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
>   }
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 0607eff5e6..cee793a440 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -237,8 +237,8 @@ static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
>   
>   static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
>   {
> -    TCGv s1 = tcg_const_tl(a->rs1);
> -    TCGv s2 = tcg_const_tl(a->zimm);
> +    TCGv s1 = tcg_constant_tl(a->rs1);
> +    TCGv s2 = tcg_constant_tl(a->zimm);
>       return do_vsetivli(s, a->rd, s1, s2);
>   }
>   
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 03773e2aa8..a563cac97a 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -300,7 +300,7 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h 
> *a)
>            * Replace bit 15 in rs1 with inverse in rs2.
>            * This formulation retains the nanboxing of rs1.
>            */
> -        mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1));
> +        mask = tcg_constant_i64(~MAKE_64BIT_MASK(15, 1));
>           tcg_gen_not_i64(rs2, rs2);
>           tcg_gen_andc_i64(rs2, rs2, mask);
>           tcg_gen_and_i64(dest, mask, rs1);