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[PATCH v4 10/36] tcg/tci: Fix big-endian return register ordering
From: |
Richard Henderson |
Subject: |
[PATCH v4 10/36] tcg/tci: Fix big-endian return register ordering |
Date: |
Sat, 7 Jan 2023 18:36:53 -0800 |
We expect the backend to require register pairs in
host-endian ordering, thus for big-endian the first
register of a pair contains the high part.
We were forcing R0 to contain the low part for calls.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 05a24163d3..eeccdde8bc 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -520,27 +520,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
ffi_call(pptr[1], pptr[0], stack, call_slots);
}
- /* Any result winds up "left-aligned" in the stack[0] slot. */
switch (len) {
case 0: /* void */
break;
case 1: /* uint32_t */
/*
+ * The result winds up "left-aligned" in the stack[0] slot.
* Note that libffi has an odd special case in that it will
* always widen an integral result to ffi_arg.
*/
- if (sizeof(ffi_arg) == 4) {
- regs[TCG_REG_R0] = *(uint32_t *)stack;
- break;
- }
- /* fall through */
- case 2: /* uint64_t */
- if (TCG_TARGET_REG_BITS == 32) {
- tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]);
+ if (sizeof(ffi_arg) == 8) {
+ regs[TCG_REG_R0] = (uint32_t)stack[0];
} else {
- regs[TCG_REG_R0] = stack[0];
+ regs[TCG_REG_R0] = *(uint32_t *)stack;
}
break;
+ case 2: /* uint64_t */
+ /*
+ * For TCG_TARGET_REG_BITS == 32, the register pair
+ * must stay in host memory order.
+ */
+ memcpy(®s[TCG_REG_R0], stack, 8);
+ break;
default:
g_assert_not_reached();
}
--
2.34.1
- Re: [PATCH v4 04/36] tcg: Introduce tcg_out_addi_ptr, (continued)
- [PATCH v4 05/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF, Richard Henderson, 2023/01/07
- [PATCH v4 06/36] tcg: Introduce tcg_target_call_oarg_reg, Richard Henderson, 2023/01/07
- [PATCH v4 07/36] tcg: Add TCG_CALL_RET_BY_VEC, Richard Henderson, 2023/01/07
- [PATCH v4 08/36] include/qemu/int128: Use Int128 structure for TCI, Richard Henderson, 2023/01/07
- [PATCH v4 09/36] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128, Richard Henderson, 2023/01/07
- [PATCH v4 10/36] tcg/tci: Fix big-endian return register ordering,
Richard Henderson <=
- [PATCH v4 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128, Richard Henderson, 2023/01/07
- [PATCH v4 12/36] tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128, Richard Henderson, 2023/01/07
- [PATCH v4 13/36] tcg: Add temp allocation for TCGv_i128, Richard Henderson, 2023/01/07
- [PATCH v4 14/36] tcg: Add basic data movement for TCGv_i128, Richard Henderson, 2023/01/07
- [PATCH v4 15/36] tcg: Add guest load/store primitives for TCGv_i128, Richard Henderson, 2023/01/07
- [PATCH v4 16/36] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128, Richard Henderson, 2023/01/07
- [PATCH v4 17/36] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64}, Richard Henderson, 2023/01/07