Re: [PATCH v6 13/13] tests/tcg/s390x: Tests for Vector Enhancements Facility 2

[Thomas Huth]

On 28/04/2022 11.47, David Hildenbrand wrote:
> From: David Miller <dmiller423@gmail.com>
>
> Signed-off-by: David Miller <dmiller423@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Tested-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
[...]
> diff --git a/tests/tcg/s390x/vxeh2_vlstr.c b/tests/tcg/s390x/vxeh2_vlstr.c
> new file mode 100644
> index 0000000000..5677bf7c29
> --- /dev/null
> +++ b/tests/tcg/s390x/vxeh2_vlstr.c
> @@ -0,0 +1,139 @@
> +/*
> + * vxeh2_vlstr: vector-enhancements facility 2 vector load/store reversed *
> + */
> +#include <stdint.h>
> +#include "vx.h"
> +
> +#define vtst(v1, v2) \
> +    if (v1.d[0] != v2.d[0] || v1.d[1] != v2.d[1]) { \
> +        return 1;     \
> +    }
> +
> +static inline void vler(S390Vector *v1, const void *va, uint8_t m3)
> +{
> +    asm volatile("vler %[v1], 0(%[va]), %[m3]\n"
> +                : [v1] "+v" (v1->v)
> +                : [va]  "d" (va)
> +                , [m3]  "i" (m3)
> +                : "memory");
> +}

The vxeh2_vlstr test fails when compiling with Clang instead of GCC ... 
seems like it enjoys using register r0 in the spots that use the "d" 
constraints in the inline assembly in here. The fix is easy:

diff a/tests/tcg/s390x/vxeh2_vlstr.c b/tests/tcg/s390x/vxeh2_vlstr.c
--- a/tests/tcg/s390x/vxeh2_vlstr.c
+++ b/tests/tcg/s390x/vxeh2_vlstr.c
@@ -13,7 +13,7 @@ static inline void vler(S390Vector *v1, const void *va, 
uint8_t m3)
 {
     asm volatile("vler %[v1], 0(%[va]), %[m3]\n"
                 : [v1] "+v" (v1->v)
-                : [va]  "d" (va)
+                : [va]  "a" (va)
                 , [m3]  "i" (m3)
                 : "memory");
 }
@@ -21,7 +21,7 @@ static inline void vler(S390Vector *v1, const void *va, 
uint8_t m3)
 static inline void vster(S390Vector *v1, const void *va, uint8_t m3)
 {
     asm volatile("vster %[v1], 0(%[va]), %[m3]\n"
-                : [va] "+d" (va)
+                : [va] "+a" (va)
                 : [v1]  "v" (v1->v)
                 , [m3]  "i" (m3)
                 : "memory");
@@ -31,7 +31,7 @@ static inline void vlbr(S390Vector *v1, void *va, const 
uint8_t m3)
 {
     asm volatile("vlbr %[v1], 0(%[va]), %[m3]\n"
                 : [v1] "+v" (v1->v)
-                : [va]  "d" (va)
+                : [va]  "a" (va)
                 , [m3]  "i" (m3)
                 : "memory");
 }
@@ -39,7 +39,7 @@ static inline void vlbr(S390Vector *v1, void *va, const 
uint8_t m3)
 static inline void vstbr(S390Vector *v1, void *va, const uint8_t m3)
 {
     asm volatile("vstbr %[v1], 0(%[va]), %[m3]\n"
-                : [va] "+d" (va)
+                : [va] "+a" (va)
                 : [v1]  "v" (v1->v)
                 , [m3]  "i" (m3)
                 : "memory");
@@ -50,7 +50,7 @@ static inline void vlebrh(S390Vector *v1, void *va, const 
uint8_t m3)
 {
     asm volatile("vlebrh %[v1], 0(%[va]), %[m3]\n"
                 : [v1] "+v" (v1->v)
-                : [va]  "d" (va)
+                : [va]  "a" (va)
                 , [m3]  "i" (m3)
                 : "memory");
 }
@@ -58,7 +58,7 @@ static inline void vlebrh(S390Vector *v1, void *va, const 
uint8_t m3)
 static inline void vstebrh(S390Vector *v1, void *va, const uint8_t m3)
 {
     asm volatile("vstebrh %[v1], 0(%[va]), %[m3]\n"
-                : [va] "+d" (va)
+                : [va] "+a" (va)
                 : [v1]  "v" (v1->v)
                 , [m3]  "i" (m3)
                 : "memory");
@@ -68,7 +68,7 @@ static inline void vllebrz(S390Vector *v1, void *va, const 
uint8_t m3)
 {
     asm volatile("vllebrz %[v1], 0(%[va]), %[m3]\n"
                 : [v1] "+v" (v1->v)
-                : [va]  "d" (va)
+                : [va]  "a" (va)
                 , [m3]  "i" (m3)
                 : "memory");
 }
@@ -77,7 +77,7 @@ static inline void vlbrrep(S390Vector *v1, void *va, const 
uint8_t m3)
 {
     asm volatile("vlbrrep %[v1], 0(%[va]), %[m3]\n"
                 : [v1] "+v" (v1->v)
-                : [va]  "d" (va)
+                : [va]  "a" (va)
                 , [m3]  "i" (m3)
                 : "memory");
 }

I'll fix it up in my queue, so no need to resend.

 Thomas